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The current signature is a direct consequence of the application profile, so the application scenario pertaining to analysis is profiled in a RTL/gate-level logic simulator. This simulation stamp is subjected to a cycle-by-cycle power analysis of the design. A worst case power cycle is selected, and for an entire cycle the transient power grid analysis is performed. This approach comprehends the transient analysis requirements. The modeling requirement for a static analysis is a much simpler subset. For 3D modeling requirements, interface ports must be defined at the silicon boundary and not at the package boundary. The switching frequency content of the logic circuit is a key parameter that will decide the complexity of the model order reduction for the SoC power grid. Since frequency response accuracy is desired in this model, frequency domain-based order methods are used for model creation. The model also complies for passivity and stability after order reduction, and is scalable with respect to power grid hierarchy. To reduce the complexity of computation by abstracting multiple power ports into one, the equivalent parasitic network and the current signatures scale accordingly. Expanding the chip power model to represent a SoC in its entirety is also possible.

This is essentially a two-step approach. A stand-alone computation is performed first, to create the chip power model of the SoC being integrated. Second, a model is included along with the external circuit-level components of the base SoC, for which the IR analysis must be performed. The external circuit-level components include the package and the board-level circuit parameters connected to the 3D system. The integration approach is illustrated here with one stacked die represented by a chip power model. The dashed line enclosure around the top die indicates it can be abstracted as a chip power model and integrated to the base die for an analysis computation.

RN732BTTD4992C10_Datasheet PDF

Static analysis In a concurrent static IR simulation, layouts for both die are included in the set-up and a combined static analysis is performed for the integrated 3D system. In a model-based static IR simulation, a chip power model is created for the top die and then integrated into the 3D framework for static IR analysis. Static analysis results are compared between the concurrent and model-based approaches. The error margin between the two types of analysis provides a perspective of the model’s accuracy. The figures show the IR drop map obtained through concurrent and model-based analysis. The worst case IR drop for the bottom die is exactly the same for the two approaches – validating the chip power model. Along with the IR drop map, cell instances with worst case IR drop are monitored for the base SoC. The top ten instances with maximum IR drop are exactly the same between the two approaches, confirming the model accuracy for static IR analysis.

Dynamic analysis Dynamic analysis results are analysed for both concurrent and model-based approaches. A chip power model is created of the top SoC for dynamic analysis mode, and analysis is performed by the model and concurrent based approaches. The following figures illustrate cell distribution of worst case IR drop in both the model-based and concurrent analysis. The distribution is plotted for the base SoC and a model-based analysis is performed, showing the distribution profile is similar between the two approaches. The order of magnitude difference between the cell counts can be attributed to the fact that in the model-based approach, there are no cell counts being accounted for the top die, but they are comprehended for a concurrent analysis. Worst case IR drop violating instances computed between the two approaches and the top 20 cell instances all match, but they are not necessarily in the same order. This again demonstrates the accuracy of the model-based approach for dynamic IR analysis.

RN732BTTD4992C10_Datasheet PDF


An order of magnitude reduction in runtime for model-based analysis is shown in the example. While concurrent analysis can take 45 minutes of elapsed time to execute, a model-based analysis is complete within 10 minutes of elapsed time.

RN732BTTD4992C10_Datasheet PDF

Apart from validating a modeling approach, analysis can also yield various insights into the power grid design. The concurrent dynamic analysis shows the top die has a higher IR drop compared to the bottom die, as power is supplied through a TSV. This also helps validate the sufficiency of power TSV structures for power distribution.

So in conclusion, using a modeling approach with an existing chip power model for package co-design analysis in a 3D-IC chip model-based voltage drop analysis, we have seen that a chip power model is accurate for both static and dynamic analysis, vis-a-vis concurrent analysis, and learned how concurrent and model-based approaches deliver both accuracy and computation time.

So what does ISO mean for the automotive engineers tasked with developing high-integrity embedded systems that must comply with the standard? Could you please talk about some of the key challenges and topics related to ISO 26262? Developing high-integrity applications in general are governed by industry standards and guidelines such as ISO 26262. This means that additional requirements on the development process need to be fulfilled. Next to extensive and systematic verification, validation and test, with the appropriate documentation of each process step, the engineers need to demonstrate overall conformance by creating a document that describes how each step in their respective development life cycle fulfills requirements defined by the standard.

Another aspect is that automotive engineers have to create the evidence that the tools they are using for developing these high integrity systems are appropriate for these tasks . To aid this, ISO 26262 defines a comprehensive tool classification and tool qualification process.

Evolving their existing development process to one that is compliant with ISO 26262 and that meets the associated tool qualification requirements for the corresponding software tools is a key challenge for engineers.

What are some strategies for developing high-integrity embedded systems that are ISO-compliant? ISO 26262 consists of 10 parts that address different aspects of the development process. In working with leading automotive companies, we have found that a best practice is to work systematically through these parts and analyze the impact that each part might have on the existing processes. Essentially, the effort involves performing a gap analysis between the standard’s requirements and existing processes and defining process adoptions that can be rolled out to the projects.

Typically, we see creation of defined groups or teams that have a division or corporate wide responsibility to assess existing processes and introduce adoptions. In addition, these groups perform a systematic tool (chain) qualification in accordance to ISO 26262.


Chapter 1, Part 1 covers scientific computation, numerical analysis and engineering; computational electromagnetics; accuracy and efficiency; programming languages; writing and debugging numerical codes; and begins the overview of EM field theory.

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