<p>The Koreans apparently are not alone in their crusade to get the study going. KSIA president Jung Hun Suh said that the European Electronic Components Manufacturers Association (EECA) is also pushing to have the dumping study relaunched. While this move came as a surprise to the Korean group, since in past years EECA has been as aggressive as the U.S. chip industry in filing various chip dumping suits against Korea, Choi believes that EECA now recognizes that uniform global dumping standards would be the chip industry's best interest.</p>

The two-chip solution includes a DSP and analog front end and has power consumption of only 800 mW. Due for third-quarter release, the first member of the Optimizer chipset family features a USB interface, which eases the deployment of DSL modems to consumer and SOHO markets.

This partnership allow our customers to quickly implement a complete solution for the recently standardized IMA format and get to the market much faster,” said Wendy Burgess, Mitel product line manager for ATM transmission components. Competing solutions involve either programmable logic, such as FPGAs, or processor-based design, such as a segmentation-and-reassembly (SAR) chip from Maker Communications Inc. (Framingham, Mass.), she said.

But Mitel figures its single-chip solutions and the Ficon software will prove to be a faster approach to launching IMA-based ATM systems. The Ficon IMA core software supports all features of the MT90220 and MT90221 chips, and it implements the features of the 1.0 and 1.1 IMA specification, including hitless add, delete and restore, asymmetrical mode, automatic fallback and restore and independent timing, according to Ficon.

RN73H2ETTD1331F100_Datasheet PDF

The IMA core software is available for a one-time license of $50,000 to $200,000 depending upon the system configuration and the number of lines, said Suresh Kabra, director of marketing at Ficon.

IRVINE, Calif. — Startup NewPort Communications Inc. made its initial product presentations to customers at Supercomm this week, and named Anil Bedi, an executive with experience in specialized processes and mixed-signal designs in stints at AMCC, National Semiconductor, and TriQuint Semiconductor, as its president.

Launched by former Rockwell Semiconductor alum Armond Hairapetian and Lorenzo Longo, NewPort has developed concepts for front-end Sonet functions involving a new design concept it calls current-controlled MOS (C2MOS). Longo said the process requires no special mask steps from a standard CMOS process, but allows high-integration analog functions for OC-48 Sonet (2.5 Gbits/second) to be implemented in a process that is no more difficult to manufacture than standard CMOS.

RN73H2ETTD1331F100_Datasheet PDF

We wanted to start with the tough problems first,” said Hairapetian, executive vice president of NewPort. This could easily be applied to serial backplane or RAID access markets, but we wanted to show that pure CMOS could address OC-48 mixed-signal designs, with all the advantages in power dissipation that implies.”

The C2MOS concept involves enough proprietary techniques that NewPort has filed for 12 patents on the process. Prototypes of first products in the process are essentially complete, and will be sampled later this summer, the company said.

RN73H2ETTD1331F100_Datasheet PDF

Not long ago, those describing the young silicon-IP market used the Wild West as a metaphor. Intellectual-property business models displayed little similarity from one day to the next, licensing contracts varied from deal to deal, and yesterday's hotshot start-up faded quickly into the sunset, overshadowed by a newer and faster gun.

Those perceptions no longer hold, according to IP providers and ASIC vendors, who maintain that things have settled down. They cite more consistent licensing procedures, less suspicion of the IP concept, and the fact that some established IP suppliers have developed a track record.

In a related announcement, Compaq Computer Corp. (Houston) said it plans to produce a Presario notebook system based on AMD's new chip.

POCATELLO, Idaho — Analog circuits remain a tough challenge for a designer of mixed analog/digital ASICs. Digital designers may feel comfortable with register-transfer-level (RTL) descriptions of digital circuits, but how well do they understand analog circuits? By letting designers cull models of precharacterized cells, the M-Smaster design system from American Microsystems Inc. (AMI) gives analog and mixed-signal design the same flow as digital gate arrays.

M-Smaster is essentially a top-down design environment for mixed-signal ASICs. It lets designers insert analog cell blocks at almost any level, to simulate the behavior of those cells with the rest of the chip and, most significantly, to assume a comfortable place in the final layout. Mixed-signal IC layout has always been difficult, especially where the analog cells are sensitive to noise and temperature variations. The methodology provided by M-Smaster improves the chance of first-pass success, said Robert Smith, director of design technology for AMI (Pocatello, Idaho).

Some tweaks” or trimming may be required for additional accuracy, but errors in the interface between digital and analog cell blocks are eliminated with this approach, he said.

Analog handoff

Chu mentioned the emergence of a cell-phone/PDA convergence” area, where InViso is focusing its efforts, and said that something similar will happen with PC monitors and TVs over the next five years. We'll see more and more home appliances used for Internet access, Web browsing and TV broadcast.”

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