H&D Wireless AB

<p>A smaller device that offers only 16 ports, the M28525, will sample next month at the same time as the M28529. Taqi Mohiuddin, product line manager for IMA devices at Mindspeed (www.mindspeed.com), said the devices will find equal interest in wireless-infrastructure applications for 2.5G and 3G networks, and in digital subscriber line access multiplexers using T1 lines as uplinks. In wireless networks, IMAs can be used in the basestation controller or metropolitan switching center gear.</p>

If you think this is just another glacially slow, incremental update, like Verilog 2001, watch out: You may get run over.

Addressing Schemes and More RLDRAM II has two addressing schemes: a multiplexed mode similar to an SDRAM's, as well as a non-multiplexed mode similar to that found on SRAM devices. In addition, other features—such as on-die termination (ODT), unidirectional data strobes for high speed and low-skew clocking, data mask capabilities that mask data on WRITE commands issued to the device, and a data valid signal that allows easy data capture and simple controller data buffer design—address both the memory requirements of today's applications, including graphics and L3 cache, and the future needs of the networking community.

Depending on the specific processing strategy, the memory bus interfacing a network processor or ASIC system in a seven-layer packet process may be required to run up to eight times faster than the link rate to enable full READ and WRITE operations and throughput. For an OC-768 application, the data rate needed may reach as high as 40 Gbit/s.

DA2421-ALB_Datasheet PDF

Comparing RLDRAM II's write-read”write access at 300 MHz to that of DDR2 SDRAM reveals the data rate of each architecture is 20.95 Gbit/s and 4.15 Gbit/s, respectively. To meet the 40-Gbit/s requirement, designers would need 20 RLDRAM devices as compared with 97 DDR2 SDRAM devices. Obviously, using the RLDRAM devices results in significant power and space savings. At 400 MHz, the number of RLDRAM II devices is reduced even further.

Figure 4 compares an RLDRAM II CIO device with DDR2 as packet memory. In this example, four 4-word bursts are read, then another four 4-word bursts are written. Each scenario makes optimal assumptions for its respective device. For DDR, this means all data comes from one open page, while for RLDRAM II, it means no bank conflicts exist.

DA2421-ALB_Datasheet PDF

As shown in Figure 4, RLDRAM II requires only 33 clock cycles to perform these operations at 300 MHz clock (600 Mbit/s data), thus achieving a bus efficiency of 97 percent (33 cycles are required to transfer 32 pieces of data). DDR2 SDRAM, on the other hand, delivered a bus efficiency of only 43 percent. (74 clock cycles are required to transfer the same amount of data).

Figure 5 compares the command and data sequencing between QDR SRAM and RLDRAM II SIO. RLDRAM II has a longer initial latency than the QDR device, however it achieves full bus utilization when refresh commands are scheduled in a way that avoids bank conflicts. Bank conflicts can also be avoided by controlling the bank sequence of data, which is difficult in some applications. A refresh operation takes the same time as any other DRAM access, one full tRC period.

DA2421-ALB_Datasheet PDF

Running RLDRAM II at 1.8V I/O makes it feasible to control either RLDRAM or DDR2 SDRAM devices. It is recommended the controller be designed with programmable impedance outputs that have either a continuously variable drive or several coarse points to select from. Also, the input receivers should be designed to operate with tight trip points. Table 1 shows a quick comparison between RLDRAM II and DDR2.

For additional information visit: STMicro or TI.

Product Bulletin

Hsinchu, Taiwan – Dec. 15, 2003 – UMC announced a breakthrough Electromagnetic Design Methodology (EMDM) for RFCMOS designs that uses a combination of electromagnetic (EM) analysis tools working in conjunction with each other to reduce simulation cycle times from hours to just minutes. UMC's new methodology, effectively eliminates what has traditionally been a tremendous time and resource intensive commitment for RF designers. The methodology was also created to greatly reduce overall development cycle times and costs for customers designing RFCMOS ICs.

S. C. Chien, division director of Central Research and Development at UMC, commented, UMC is constantly seeking ways to better enhance the services available to our customers. With our innovative EMDM, the learning curve for 3D EM simulation tools has totally been eliminated. The inductor simulation process can now be thoroughly completed in as little as 20 minutes with a few clicks of a computer mouse, allowing UMC RF customers to realize a significant advantage over their competitors not using UMC's EMDM.”

While most silicon foundries are still struggling to provide reliable, accurate RFCMOS design models and passive component libraries, UMC's EMDM includes process-related information for EM simulation, allowing customers to design their own inductors with fast, accurate, and low-cost features. EMDM includes the use of a variety of industry-recognized electromagnetic analysis tools, including Ansoft's leading HFSS 3D simulation software.

Vad är då skälet till att selektiv våglödning har fått en så stark ställning i Sverige?

Copyright © 苏ICP备11090050号-1 tl431 datasheet All Rights Reserved. 版权投诉及建议邮箱:291310024@725.com