Radio Bridge Inc.

<p>At the end of the first quarter of 2003, we have seen Arrow make yet another acquisition, this time the industrial distribution business of Pioneer-Standard. What is occurring now is a consolidation at the upper levels of the distribution business, separating further the giants from the balance of the distributors. As our industry continues to use contract manufacturers as the low-cost manufacturing model, the giant distributors are insatiably going after that large market of business. And if truth be told, and they had their way, to the exclusion of all of the remaining midsize distributors.</p>

Algorithmic estimation and optimization are followed by the creation of a power optimal architecture. This includes memory architecture, scheduling, number and types of resources, how those resources are shared and bound to the algorithm operators, type of data encoding, controller design, floor plan and clock tree design.

Fundamentally, the technology is based on thick oxides for charge transfer, which assures future scaling capability. The coupling (floating) gate oxide is never subject to a high electric field stress (strong coupling to high-voltage node); thus, remains reliable during the life of the device. The SoC development cycle time and cost is reduced because the simpler design results in easier debug effort, reduced test and faster yield time.

This is our third installment in the look at the impact that jitter will have on emerging 5- to 6.25-Gbit XAUI backplane designs. In Part 1, we examined how designers can analyze backplanes in the time and frequency domains. In Part 2, we looked at the impact of deterministic jitter and receive-end equalization on designs. Now, we'll provide a set of practical test platforms for evaluating next-generation platforms.

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It's important to note that in this article real channels were used in conjunction with an active receive equalization device to examine the impact of various passive characteristics on the performance of the channel/equalizer combination. S-parameter measurements of the channels under consideration will be presented to provide a qualitative understanding of channel variance. Quantitative analysis using tools that accurately predict channel performance out to a bit error rate (BER) of 10-12 were also performed on channels running at 5 Gbit/s.

Passive, Active Interactions To better understand the interactions between passive and active components, we've set up test platforms that present various channels to an equalizer and analyzes the jitter content at its output. The basic set-up is shown in Figure 13 . Three different test platforms were used that consisted of various materials, trace conditions, layer connections, and board thicknesses.

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For the purpose of this paper two basic platforms were chosen. A Material variation of one platform was also used in order to include the effect of material changes.

Platforms 1 and 2 were set up to show interoperability between the XAUI and HM-Zd backplanes. These are the same, with the Platform 1 backplane being composed of Nelco 4000-2, and the Platform 2 backplane being composed of Nelco 4000-6. A conceptual diagram of these platforms is shown in Figure 14 .

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The platform shown in Figure 14 consists of two line cards that provide SMA access and the Z-PACK HM Zd based backplane. Each line card is 0.093-in. (nominal) thick and consists of 14 layers. Note: platform 1 is fabricated using Nelco 4000-2 material.

Enforcing the rules

Even though you may connect two OTG-enabled devices, PDA to PDA for example, and both are capable of acting as the host, there is only ever one host at any given time. Just because OTG devices can swap modes does not mean you can change the basic rules of USB connectivity. This is a common misunderstanding of OTG and leads to much confusion over required functionality and the applications for which it is applicable. It is easiest to explain, and enforce, the connection rules for USB through the connectors and cables defined by the standard.

USB 2.0 introduces some new nomenclature to describe the role of a given device. Host devices, such as PCs, are defined as A devices while peripheral devices, such as mice and PDAs are defined as B devices. The specification also defines standard-A, standard-B and mini-B connector pairs as well as two cables to connect both the B types to A. These are the most commonly used connectors today, with the standard-A found on PCs and hubs, standard-B on many office products, such as printers, and mini-B common on portable devices like PDAs and DSCs.

The OTG supplement adds the mini-A connector pair and the mini-AB receptacle only (no plug). The mini-A and mini-B plugs are keyed so that they can only accept their corresponding receptacles, while the mini-AB receptacle can accept either a mini-A or mini-B plug. OTG also defines two new cables to connect the B-types to the new mini-A. The mini-A receptacle is defined for use in adaptor cables only but could find a niche in small form-factor computers, such as pocket PCs, that may be USB hosts but not adopt OTG.

OTG defines a new pin in the connection, named ID, which is used to signal required host behavior in an OTG system. In the standard A and B connector pairs the pin is absent, because they pre-date the supplement. In the mini-B it is left unconnected because the connector was designed with the upcoming OTG specification in mind. In the mini-A plug it is shorted to GND and in the mini-AB is used to determine the nature of the connection.

Following synthesis, power-aware mapping techniques may be used to optimize the netlist. These techniques include mapping highly active nodes into specific cells and mapping highly active input signals onto low capacitance input pins. When partitioning the design into multiple voltage (VDD ) domains, appropriate level shifter elements need to be inserted into the netlist to connect logic elements across multiple domains. Furthermore, signals to and from domains that may be switched on and off require special attention so as to avoid any floating net” problems.

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