Boeing Co. recently insisted that the new battery design for its 787 Dreamliner eliminates the possibility of fire.” That may have pacified the average consumer, but it hasn't made engineers very happy.

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<p>The Crusoe, introduced in January last year, uses elaborate software instructions rather than hardware to perform certain functions. Low power consumption means it emits less heat that other chips, so more can be put into a given space. Ditzel said it was too soon to give a revenue forecast for Transmeta's server-related business, although it could be a significant contributor by the second half of this year.</p>

Boeing Co. recently insisted that the new battery design for its 787 Dreamliner eliminates the possibility of fire.” That may have pacified the average consumer, but it hasn't made engineers very happy.

There are many, many walls,” he said. The lithography is very important and difficult. If the 50-nm nodes must be ready by 2007, then we must have the tools available by 2005.”

And while Setoya did not suggest that the Mirai project was underfunded, he said ASET was anxious to get the fullest budget appropriation possible.


Of course, we can accelerate the speed if more money is put in,” he said. Of course we are asking for more!”

Programs criticized

The past few years have seen increasing criticism here of national technology programs sponsored by the Japanese government, coordinated by ministries, and realized by industry, for such programs' perceived failure to meet modern real-time business needs, internal wrangling, and lack of clear objectives. Earlier this month at the Industry Strategy Symposium Japan 2000, leading semiconductor and electronics company executives criticized this stasis approach. Rebuking what is sometimes called the iron triangle” of government, bureaucrats and industry, Sony Corp. president Nobuyuki Idei called for more flexible approaches to create next-generation technologies and products.


More directly, Nippon Foundry Inc. president Yukio Sakamoto directly criticized Semiconductor Leading Edge Technologies Inc. (Selete), the METI-backed research project to develop system-on-chip technologies, and Asuka, a Mirai counterpart that seeks to develop process technologies beyond the 100-nm node, as potentially ineffective.

There are 11 companies doing this Asuka project; that's a tall order,” Sakamoto said. The maximum number should be three. It will be very difficult to make this a success.”


Responding to Sakamoto's comments at ISS, Setoya said, Maybe it is a reaction to the perception of bureaucracy. We must avoid this and encourage and promote actual results.” Setoya suggested that ASET was keenly aware of the need for efficient coordination between various agencies.

More pertinently, Setoya said, the Mirai program must deliver the results of each phase of its basic research to the Asuka program for implementation. ASET plans to sponsor joint meetings with Mirai and Asuka officials to adjust each parties' research programs, he said. The five-year Asuka project is due to deliver evaluations on 100-nm node technologies, including lithography, CAD and interconnect processes, in fiscal 2003.

At the higher signaling rates, embedding the clock with the data has significant advantages. Rather than send parallel clock and data signals, with the attendant danger of the clock getting out of phase with the data, Daane said, With CDR the clock skew is minimized and frequencies can be turned way up, the trade-off being that it is a more complex design.”

Accelerant tackles backplane

While Altera's programmable devices offer customers flexibility, other companies are zeroing in with parts that promise to relieve network bottlenecks at the backplane. Accelerant Networks (Beaverton, Ore.), for example, has chosen the backplane transceiver market as its target, according to chief executive officer Paul Nahi.

The bottleneck inside the network has moved from the box-to-box pipes to the challenge of what to do with the data once it gets into your box. The bottleneck that was on the WAN has moved to the backplane,” Nahi said.

While Accelerant Networks won't see its first silicon until May and won't ship commercial products until September or later, Nahi claims that his company is unique in targeting very high-performance backplanes.

Paul Otellini, executive vice president and general manager of the Intel Architecture group, claimed that the new 64-bit McKinley version will be several times faster in performance than the initial Itanium chip. He said an entirely new (chip) platform will be introduced” after McKinley with the next generation Infiniband I/O an integral feature. This is expected to be the 64-bit chip code-named Madison, to be produced on Intel's new 0.13-micron process.

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