GEMS Sensors

<p>The final step in production is high-voltage and parametric testing. Analog Devices employs three procedures to bring quality close to Zero ppm. First, test coverage is expanded by adding extra tests under different supply conditions. Second, testing is performed at different temperatures, similar to qualification testing described above. Third, Analog Devices employs part average testing, or PAT. This allows us to reject parts that seem good but which may be outliers. PAT works by looking at the distribution of a parameter and rejecting parts that fall outside the distribution for that wafer even if the parameter is within the limits. This is shown in the figure below where three batches each have distributions with different means and spreads. Outliers, or maverick” parts, are shown as falling outside their corresponding distribution (shown by color) but still well within the production test and data sheet limits. In normal practice, without PAT, these parts would be shipped to customers and may never exhibit any defects; however, where Zero ppm is essential, the additional test time and yield loss warrant this extra step. </p>

Data usage estimates are provided to complement the code footprint discussion. There are multiple modules requiring data to operate as shown in Table 3-5. Many of the data sizes calculated in the following sub-sections assume 4-byte pointers. The data requirements for each of the objects must be added, as needed by the configuration of the TCP/IP stack. The configuration of the objects is represented in a formula for each. The equation variables all in upper case are #define configuration parameters found in Appendix C, µC/TCP-IP Configuration and Optimization” on page 701. Calculation methods follow. BUFFER REQUIREMENTS

The market research firm has ranked manufacturing companies by their installed capacity in four categories. At the leading edge (below 40nm) Samsung leads followed by Intel, Toshiba/SanDisk, SK Hynix and Micron (see figure 2). The ranking reflects the significance of memory to production volumes, but not necessarily revenues.

IC Insights has divided global installed capacity, as of the end of 2012, into six categories based on the minimum geometry of the processes used in wafer fabrication. About 27 percent of global wafer capacity was for devices having geometries smaller than 40nm (see figure 1). Such devices include high-density DRAM, which are typically built using 30nm- to 20nm-class process technologies; high-density flash memory devices that are based on 20nm- to 10nm-class processes; and high-performance microprocessors and advanced ASIC/ASSP/FPGA devices based on 32/28nm or 22nm technologies.

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About 22 percent of global capacity is dedicated to mature” process nodes at 90nm, 0.13-micron, and 0.18-micron. A variety of processes base on these nodes are offered by foundries including TSMC, UMC, GlobalFoundries, SMIC, and TowerJazz.

Although the leading-edge of chip manufacturing has, up until now, been moving in line with Moore's law the business has a long tail and large quantities of standard analog and general-purpose logic are manufactured with well-established process technologies having larger than 0.4-micron feature sizes. In addition, high-voltage power semiconductors require large-geometry process technologies.

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