H&D Wireless AB

<p>Cisco intends to work with Intel to extend the cable industry's DOCSIS specification to include Intel's USB cable modem specifications as an alternative to today's Ethernet interface for cable modems. Intel will provide engineering and marketing resourcesto develop, validate and promote its USB alternative for DOCSIS-compliant cable modems. Cisco will work with Intel to enhancethe DOCSIS specification and validate the end-to-end capability.</p>

Net sales for the quarter of $51.1 million increased 18 percent when compared to net sales for the prior quarter of $43.4 million, and declined 24 percent when compared to net sales of $67.2 million for the comparable quarter of fiscal 1996. Net sales for the first nine months of fiscal 1997 were $134.7 million, a 31 percent decrease as compared to $194.6 million for the same period a year ago.

The Voyager Series of VHDL simulation products includes Voyager VS, a VHDL software simulator; Voyage CS, a mixed-level software simulator; and Voyager CSX, a mixed-level software simulator with seamless integration to NSIM, Ikos' second-generation hardware accelerator.

Voyager VS sells for $9,500; Voyager CS sells for $22,000; Voyager CSX sells for $27,000. All prices are United States list prices.

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Ikos Systems 19050 Pruneridge Ave. Cupertino, CA 95014 (408) 366-8535 http://www.ikos.com

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San Jose–Aug. 25, 1997–A multi-million dollar agreement signed last year between Motorola Semiconductor Product Sector (SPS) and Cadence Design Systems Inc. (San Jose) has resulted in the delivery of Motorola's SCORPION multimedia chip.

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This agreement extended Motorola's relationship with Cadence by standardizing its design teams on Cadence's Alta application-specific, system-level methodology for the design and creation of wireless and multimedia systems-on-silicon and chip sets. Motorola is using the Alta SPW environment as a vehicle to accelerate the delivery of system-level digital signal processing core models. This adoptation has been key to Motorola's development process and ability to service it's customers.

Motorola SPS's SCORPION project was completed in approximately six months using Cadence's Alta system-level methodology. The SPW design environment was used to create and test a virtual prototype of the Motorola Graphics Engine chip before implementation. The original Graphics Engine design was targeted to a FPGA, placed on a printed circuit board for rapid prototyping and run in a test facility. Testing involved a real video source feeding the design while designers verified the image on screen. Once designers were satisfied with the design, it was retargeted.

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Because the SPW design environment supports parameterized libraries, the development team was able to reuse portions of the previous design of the Graphic Engine. SPW provided the front-end environment to capture and reuse specific blocks from the Graphics Engine to simulate the entire SCORPION chip, and then to generate VHDL or Verilog HDL for synthesis. From synthesis, the design was targeted to a Motorola submicron technology.

The completion of the SCORPION project underscores Motorola's ongoing commitment to Cadence's Alta system-level design methodology. The methodology has been used successfully within Motorola for virtual prototyping before silicon implementation and design reuse, as well as for intellectual property delivery to customers.

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Wilsonville, Ore.–Sept. 15, 1997–Mentor Graphics Corp. (Wilsonville) and Denali Software Inc. (Palo Alto, Calif.) announced a partnership providing worldwide availability of Denali Software's Memory Modeler, which enables designers to quickly generate memory models required for logic simulation. Mentor Graphics will distribute Memory Modeler through its worldwide sales and support organization, having designated Memory Modeler its preferred memory modeling solution.

Memory Modeler currently supports a multitude of memory types, including DRAM, SRAM, SGRAM, SSRAM, FLASH, PROM, and FIFOs. Each memory type includes, on average, 12 significant configuration parameters critical for accurate system verification.

Memory Modeler automatically generates memory models by using configuration information provided by the designer. Following an input session, a fast, memory-efficient and error-free model is generated. Rapid model generation supports quick evaluation of multiple memory options in search of the optimum configuration. Traditional methods cannot address the rapid design iterations made possible by Memory Modeler.


The EPC1441 will be available in Sept. in 32-pin TQFP, 8-pin PDIP, and 20-pin PLCC packages. The 100-unit price is $3.50 each. Volume pricing for the EPC1441 is expected to be $1.50 each in the second half of 1998.

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