International Components Corp.

<p>The on-board Firewire interface is capable of streaming data at up to 32 Mbytes/s and can be used to establish a high-bandwidth serial communications link with PCs or other embedded equipment.</p>

Already, chip sales to Asia are 38 percent of the total, approximately doubling in the last five years, and non-Asian companies are scrambling to understand and compete in Asian markets against local chip suppliers.

On the receive side, the SureFyre has a guaranteed sensitivity of -70 dBm and a noise figure of 8 dB in the radio. With these two figures we're up to 7 dB better than the 802.11 specification,” said Roberts. And with an external low-noise amplifier, you can get an additional 1 to 2 dB decrease in the noise figure.”

SureFyre also offers per-carrier and per-packet equalization and per-packet antenna diversity, which collectively improve sensitivity by about 10 dB. We have good tolerance of multipath [interference] indoors, with a delay spread of 150 ns,” said Roberts. Customers really want to see [WLAN technology] cover whole homes.”

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The dual-band 802.11a/b/g chip, called TwinFyre, does all the baseband processing in the same PHY as SureFyre but uses a separate commodity radio for the 2.45-GHz 802.11b/g component. The b/g radios are getting quite inexpensive so you can combine the two,” Roberts said.

Both chip sets are built in a 0.18-micron RF CMOS process by Taiwan Semiconductor Manufacturing Co. Ltd. The SureFyre is sampling now, with volume production scheduled for the first quarter at less than $20, including the power amp. The TwinFyre will sample by the second quarter of next year, with production scheduled for the third quarter.

Wayne, N.J. – Mindspeed Technologies Inc. will expand its network-processing offerings this week with four chips and firmware that can handle traffic management and Layer 2 internetworking in core, metro, access and enterprise equipment.

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Since acquiring network processor vendor Maker Communication Inc. in 2001, Mindspeed has focused much of its packet-processing efforts at asynchronous transfer mode functions like segmentation and reassembly. Now, with the release of the TSP3 family, the company adds support for packet and cell-based traffic patterns.

The four TSP3 devices are the M72480 for OC-3 designs, M27481 for 2xOC-3, M27482 for OC-12 and M27483 for OC-48. Mindspeed's PortMakerIII firmware lets these traffic-management chips handle Ethernet-enabled and cell traffic management plus Ethernet-to-ATM bridging.

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On the traffic-management front, the TSP3 family is designed to provide quality-of-service and class-of-service to packet networks by offering flow-based packet management, cell traffic management, Internet Protocol QoS, shaping and scheduling, said Preet Virk, director of marketing in Mindspeed's Broadband and Internetworking Systems unit. The devices also provide the ability to pack frame relay, ATM and Ethernet traffic onto an IP/multiprotocol label-switching (MPLS) network or to bridge Ethernet services over ATM links, Virk said.

To deliver these capabilities, the devices come with either one or two Octave processor cores; a content descriptor lookup (CDL) engine; a context cache and data RAM; a traffic-scheduling system; and a buffer-management engine.

In July, Rambus took off the wraps and provided more details of its next-generation memory interface technology, formerly known as Yellowstone. Rambus, along with Japan's Toshiba Corp. and Elpida Memory Inc., rolled out the technology, now called XDR DRAM.

Running at 3.2-GHz, XDR DRAM offers eight times the bandwidth of today's PC memory, according to the Los Altos, Calif.-based company. Toshiba Corp. and Elpida Memory Inc. expect to begin shipping XDR DRAM in 2004, ramping to volume production in 2005. Samsung Electronics Co. Ltd. has also licensed the technology ( see July 10 story ).

Rambus has defined all of the ingredients to bring XDR to PC main memory. These ingredients include a broad range of XDIMM memory modules, programmable-width XDR DRAMs, buffers, connectors, clock generators, and comprehensive system design guidelines and documentation.

Today's PC main memory systems are performance limited due to their use of single-ended signals and multi-drop data busses,” said Laura Stark, vice president of the Memory Interface Division at Rambus, in a statement. Differential signaling and Rambus's novel Dynamic Point-to-Point module upgrade technology allow users to maximize capacity in their memory systems without compromising performance.”

Separately, Rambus and Toshiba Corp. will jointly demonstrate Toshiba's ASIC evaluation chip that incorporates Rambus's parallel logic interface, codenamed Redwood.

The future for micro architecture development is very bright,” said Fred Weber, chief technology officer of Advanced Micro Device's computer CPU group.

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