Surge Components

<p>Flextronics' acquisition of Dii, a major industry player with services in communications, industrial instrumentation, office automation, mainframes, and servers, is set to change that.</p>

These sort of integrations are going to become more and more in demand, and that's where we need to continue our development,” he added.

Meanwhile, CynApps is add-ing VHDL-like macros to Cyn++. When using this pre-processor, designers can choose macros such as entity,” event,” and process.”

With this, a VHDL designer can use our solution to model, simulate and verify an ASIC design,” said Jim Cardwell, vice president of marketing and sales at CynApps. However, he noted, the company is not offering a C++-to-VHDL synthesis solution.

SDWL1005C19NJSTF_Datasheet PDF

To provide potential users with a lower price point, CynApps is unbundling its Cynthesis C++-to-Verilog synthesis tool from its simulation-related offerings. A $25,000 package includes CynLib support, Cyn++ and the Cyntax lint tool. Packages with Cynthesis start at $100,000. CynLib can be downloaded under an open-source license from CynApps.

WASHINGTON ( ChipWire) — The International Electron Devices Meeting, which convenes here this week, will take up the increasingly serious question of just how far solid-state electronics can be pushed before reaching the limits of physical speed and size.

In an effort to answer such questions, IBM Corp. will show a 50-nm device with what it claims is the fastest CMOS switching performance to date, and Intel Corp. will describe a device made at 0.10-micron design rules. Lucent Technologies Inc.'s Bell Labs, for its part, will present a vertical transistor” that could eventually succeed today's devices and could resolve some of the lithography and materials problems of scaling CMOS to deep-submicron territory. That's significant because some researchers now predict a breakdown in gate oxides at the 130- to 100-nm level.

SDWL1005C19NJSTF_Datasheet PDF

This year's IEDM is the 45th such conference, and the 220 papers presented over the three days from Dec. 6-8 will offer attendees a look at some of the most creative work being conducted in the world's semiconductor research laboratories.

A late paper from IBM's Watson Research Center in Yorktown Heights, N.Y., describes devices fabricated at 50-nm design rules that were created with very low threshold voltages. The low-Vt devices were used to create a 101-stage CMOS ring oscillator, which has a gate delay per stage of 6.4 picoseconds at -100C — the fastest CMOS switching performance reported to date.

SDWL1005C19NJSTF_Datasheet PDF

At room temperature, the low-Vt devices operate poorly, but when taken to -100C, performance is twice that of comparable room-temperature devices. Low-temperature CMOS has current-on and current-off characteristics that cannot be duplicated at room temperature, IBM researchers said.

Intel researchers will present some of the fastest CMOS transistors ever created. Using 0.10-micron (100-nanometer) design rules in a 16-Mbit SRAM learning vehicle,” the researchers achieved speeds exceeding 1 GHz. Power consumption was kept within acceptable limits, even with drive currents of 1 microamp per micrometer for the n-channel MOSFET and 0.45 microamp for the p-channel MOSFET.

The end result of the delays and acquisitions is that Cisco Systems is under less pressure to upgrade its Giga Switch Router line than venture capitalists warned only a year ago. Cisco has adopted a slow and steady strategy for expanding feeds and speeds for the routers used in public network backbones. With the terarouter on autopilot, Cisco has been aggressive in working on wave-division multiplexing interfaces for routers and on acquiring such optical specialists as Cerent Corp. and Monterey Networks Inc.

That may prove a smart move. Because carriers are anxious to move to packet-over-wavelength technologies, some market analysts suggest that if delays keep core routers out of the market too long, optical add-drop multiplexers or optical cross-connect systems may replace those routers in the backbone.

Not surprisingly, executives at core router companies strongly reject that view.

The integration of optical node and packet routing functions comes down to a question of economics, and the jury is still out on what kind of partitioning is most cost-effective,” Chadwick said. Avici and its primary competitors all are very interested in integrating optical functions where appropriate, but we're not worried about being swallowed by optical nodes. An optical cross-connect [OXC] clearly is better than a Sonet-layer add-drop multiplexer, and it may replace all Sonet terminals over time, but it's not clear at all that an OXC will ever replace a core router.”

Optical backplane interconnect

This experience — how CMC came by it, and how both its training and call center services interact and develop each other in refining and improving performance — exemplifies what makes the firm unique among training and outsourcing companies.

Copyright © 苏ICP备11090050号-1 tl431 datasheet All Rights Reserved. 版权投诉及建议邮箱