<p>As further evidence of the financial commitment being made to information security, the number of companies that dedicates at least some portion of their IT budget to security training or certification continues to rise. More than two-thirds (68 percent) allocate at least some portion of their IT budget to security training or certification, up significantly from last year (55 percent).</p>

Balanced Signaling

LVDS specifications allow the differential output of the LVDS source to be anywhere from 247 to 454 mVpeak . Other combinations are possible for increasing or decreasing the LVDS drive strength and voltage levels that are still within the TIA/EIA/ANSI-644 LVDS specification. You can select these features from the beginning of system concept to save power. Alternatively, they can be used simply as insurance in the event LVDS signal integrity issues are unexpectedly discovered.

These features have the potential to save a great deal of time and money in board debug should issues arise. Look carefully at the voltage levels required by the LVDS receiving device. Because every board is different, you may need to program the ADC to adjust the LVDS output levels. This is to maintain the allowable range at the LVDS receiver after board signal losses are characterized and taken into account.


Built-in test patternsThe ADS6445 provides several built-in test patterns that can be enabled in the absence of an analog input source. These can be used during initial board debug to study the timing relationship between the ADC and the FPGA, in order to determine the proper clock-to-data relationship at the FPGA interface. This ensures good timing (typically, timing can be adjusted within the FPGA LVDS inputs).

One benefit of using a built-in training pattern, compared to supplying an analog signal, is that the pattern is consistent. This eliminates any question of error coming from the analog source, making the experiment repeatable and easier to set up. The training pattern also can be used as part of a board functionality test during board manufacturing and test.

Signal gain, SNR, and SFDR Programmability can do more than solve board-level interconnect issues. Some features are designed to allow system performance tradeoffs. For instance, the ADS6445 also has internal analog-input signal-gain functions that allow you to trade off SNR for improved SFDR, or simply to lower the analog-input amplitude. A smaller input signal usually provides better distortion from the analog components prior to the ADC, and within the ADC itself.


The ADS6445 contains both coarse and fine gain options. In either case, the analog-input voltage level must be reduced by at least the amount of gain selected in the ADC. This keeps the ADC's input voltage range from saturating and clipping the digital output word. Therefore, if you want to explore using the gain settings in the ADC, plan to reduce the analog input-signal levels at the board level in the analog circuits prior to the ADC.

In Figure 3 and Figure 4 , the tradeoffs are visible between input signal level and distortion (or specifically stated here as SFDR) using two different gain-adjustment methods.


The alternative approach to the post facto verification that is built into the V design process is to specify systems as executable architectures. And, in parallel, to build a verification process based on simulation of use-case scenarios from which test cases are derived. As the specifications are mapped iteratively to models of physical systems, so test cases that address the additional structure, function, and timing of the mapped models are accreted to those already developed.

This methodology is a highly efficient concurrent architecture and verification process enabled by model-based design together with a coherent process of mapping specification and architecture to physically realizable design. There remains a vestigial tail of the V process in the physical (manufacturing) supply chain, but with a twist—the validation of manufactured subsystems and systems is achieved when all of the applicable tests generated during concurrent design and verification are applied, and the responses conform to the validation responses constructed during specification and architecture.

Recent breakthroughs in system simulation that use cheap and available multi-core host computers connected by high performance (mainly, low latency rather than high throughput) interconnect fabrics have enabled the simulation of models of very large systems with high accuracy and performance. These modeled systems can be subjected to exhaustive experimentation, using design of experiments standard methodology and multi-variate statistical techniques to simplify the analysis, to yield demonstrably correct and optimal architectures before being reduced to physical implementation. This procedure is the reverse of the current practice of build, then verify.

The relationship between supply chains and system architectures is intimate.An abstract architecture defines, in part, the structural relationships between the entities (subsystems and components) that will be assembled into a system. This approach applies whether the relationships are based on composition (vertical—forming hierarchies; horizontal—forming sets), communication interfaces, or interconnect fabrics. The building of the entities and their (progressive) integration into a system—while observing the rules of composition, communication and interconnection—is what a manufacturing supply chain does.

An architecture also defines the function and timing of:

Discharge current The discharge current is implemented with a resistor. When the comparator is high, it engages a switch to connect the discharge resistor. The comparator will cycle high and low in some ratio, attempting to keep the integrating capacitor voltage equal to the reference voltage. The percentage that this comparator is high is defined as its DensityOut . The charge is only removed this percentage of the time. The current is shown by Equation 2 :

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