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<p>Static power dissipation also has an exponential dependence on the switching threshold of the transistors (Vt ). To address low-power designs, IC foundries offer MTCMOS technologies that enable multiple-Vt libraries. This means that each type of logic gate is available in two (or more) forms: with low-threshold transistors that switch quickly but have higher leakage and consume more power, or with high-threshold transistors that have lower leakage and consume less power but switch more slowly.</p>

The problem is that compiler optimizations often depend on the compiler understanding” the intent of the code—and inline assembly can interfere with that process. For example, an inserted assembly instruction might store data to memory, so the compiler may have to assume that all variables could be modified by the in-line code. This can interfere with the compiler's ability to keep variables in registers.

To find interval 2's ID /VDS overlap power loss, we need to know the time spent in interval 2 (t2 ). t2 is the exponential rise of the gate voltage as the gate capacitance (CGS + CGD ) charges through RD + RG . In this interval (CGS + CGD ) is given in the MOSFET datasheet as CISS usually in the electrical table or as a plot of CISS vs. VDS . Alternatively, CISS can be derived from the QGS term since most of the charge goes into CGS until VGATE reaches VGP .

Approximating VGATE's rise as a first order RC results in t2 becoming,

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This results in

Solving for t2 requires finding values for VT and VGP .

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VGP as mentioned before is the Miller plateau voltage. This is named for the Miller effect, which describes how a capacitor with both terminals simultaneously changing in voltage is replaced with an equivalent capacitor where one terminal is fixed. For instance, VGS is considered constant during interval 3. VDS on the other hand changes from VIN to IOUT x RDS_ON (≈ 0). The net voltage change across the gate to drain capacitance (CGD ) will be (VIN ) + (VGS2 – VGS1 ). Using the Miller effect, the equivalent CGD referred to the source would beCGD (EFF) = CGD x (1+(VIN )/(VGS2 -VGS1 )).

Consequently, CGD appears as a much larger capacitance as seen from the gate since VGS changes little during the interval. Additionally, CGD increases dramatically with decreasing VDS (see graph of CRSS vs. VDS in MOSFET datasheets). This results in CGD swamping the gate driver.

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Before we can find a value for VGP we'll first need to know the threshold voltage VT . Typically VT is given in the MOSFET datasheet as a minimum, and thus not well defined. A more accurate value can be derived from the Typical Transfer Characteristic graph included in the MOSFET datasheet. From the transfer characteristic plot, pick 2 separate VGS values and their corresponding ID . With both sets of ID and VGS values obtain two MOSFET saturation equations

Optimum gate drive voltage: The Gate drive voltage amplitude controls the switching performance of a MOSFET in the following ways:

There is optimum Gate drive amplitude that would satisfy all of the above conditions and yields the highest ζ . This can be determined by experimentation with different voltage amplitude to determine the point of best performance. Figure 7 shows a 3D graph of the optimum Gate Drive voltage on the Z-axis as a function Drain current on the X-axis and the switching frequency on the Y-axis based on the mathematical solution of the problem. It is clear that the Gate Drive voltage must never exceed the datasheet recommended levels for high reliability operation.

Optimum power source input voltage: The industry standard in the power source input voltage for DC-DC converters for the PC market is 12Volt, but is it the optimum level? To help us answer this question, let us look at the effects of the input voltage on ζ as follows:

The optimum input voltage may be derived experimentally or mathematically. Figure 8 shows a 3D representation of the optimum input voltage on the Z-axis as a function of the load current on the Y-axis and the switching frequency on the X-axis.

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In this two part series we describe the design an embedded Asterisk PBX using the Analog Devices Blackfin processor and Silicon Labs line interface hardware. This approach has many advantages over the PC & PCI card approach including small form factor, low power consumption, and verylow cost. However it also has some challenges, for example small memory and CPU resources, and a relatively complex development environment.

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