Contelec

<p>The new supplier enabled by the iPod Video is Broadcom. Its BCM2722 facilitates the video decoding and processing.</p>

However, the first model of the class D amplifier did not function in the lab due to capacitive loading of the comparator MAX942, which is not modeled in PSpice. Since propagation delay is increased by capacitive loading, the comparator is unable to switch on and off at a high frequency. The second model of the class D amplifier solved the problem of capacitive loading by introducing the MOSFET gate driver. However, there is a significant amount of distortion at the output, which cannot be eliminated. Therefore, this model is not suitable as an audio amplifier. Improvements can be made by reducing delay time and eliminating shoot through current. Efficiency can be improved if the gate driver could provide a negative output voltage. In conclusion, the class D amplifier presented needs significant improvements before it can be used for audio purposes. However, Class D amplifiers have the potential to have 100% efficiency and therefore, are strong candidates as solutions for portable devices.

If the POL converter has an output voltage droop characteristic, it is applied now. The VOUT_DROOP coefficients are always greater than or equal to zero, and droop is only applied if the output current is greater than zero. The value of the VOUT_DROOP coefficient and the value of output current are multiplied and the result is always subtracted from the voltage command. VOUT_DROOP can only act to reduce the output voltage – never to increase it.

The next step is compare the commanded voltage developed so far with the maximum permissible output voltage set by the VOUT_MAX command. If the calculated voltage command would create an output voltage greater than the VOUT_MAX value, the POL converter limits the command voltage passed to the controller to the VOUT_MAX value, and also sets an alarm.

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The same scaling factor that is applied to the external output voltage by a resistive divider is now applied to the calculated voltage command. This is done by multiplying the calculated voltage command by VOUT_SCALE_LOOP. At this point, the converter has a calculated value that is used as the equivalent to the reference voltage in a standard analog controller. This is the value to which the converter’s duty cycle.

For setting the output voltage, and related commands like setting the output overvoltage fault threshold, the PMBus allows up to sixteen bits of resolution. For other data, like reading back the input voltage or the output current, the PMBus specification allows up to ten bits of resolution. Ten bits of resolution corresponds to a resolution of approximately ±0.05% which is more than sufficient for the vast majority of the market.

Ease of implementation The rich command set of the PMBus protocol enables designers to write lean and efficient power management programs – and implement the scheme – very easily and quickly. Voltage sequencing of POL converters provides an ideal example. Until now, many designers have chosen to use some of the excellent special-purpose controller ICs that are on the market to handle this task, accepting the fact that this involves developing programs using software provided by the IC manufacturer and using up valuable board space for the devices. Converters that can be directly controlled by PMBus potentially offer a more cost-effective and flexible solution, enabling a wide range of operating parameters to be changed at any point during the product’s life cycle, to accommodate engineering changes.

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Only two PMBus commands are required for controlling the start-up sequence of a POL converter, as shown in Figure 4. TON_DELAY programs a time for the converter to wait until starting to produce an output, and TON_RISE programs the time for the output to increase from zero to the final programmed value. The user simply programs each converter with its own turn-on delay time and turn-on rise-time. Similarly, only two commands (TOFF_DELAY and TOFF_FALL) are required for turn-off sequencing.

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Voltage margining is another area where digitally programmable converters will make life considerably easier for designers – and production test personnel. Many board manufacturers now use this technique to evaluate the performance of ICs in the face of minor variations in their supply voltages; any marginal or below-spec devices can then be replaced as part of the normal production test process, before they become expensive, difficult-to-rectify field failures. Until now, margin testing has been a highly iterative and time-consuming procedure, involving fitting different value resistors to dc-dc converters in order to vary their output voltage a few percent either side of nominal. Using PMBus-compliant POL converters, this process becomes extremely simple. Two commands, VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW, are used to pre-program the margin voltages. Then, as shown in Figure 5, using just the OPERATION command, each converter can be instructed to deliver tightly-controlled test voltages, while the effect on board performance is monitored. This can significantly reduce production test times, help eliminate ambiguity, and produce clearly documented test results.

Design options Traditionally, network equipment designers opted to perform statistics operations in software. This task was usually managed by a general purpose CPU or NPU core packet processor, and supported by external SRAM.

As long as data rates remained relatively low, the approach performed well. However, as network line rates rise, the limitations of traditional load/store architectures are increasingly apparent. In this topology, the core packet processor must fetch data from off-chip memory, perform such appropriate arithmetic operations as an increment, decrement or add a counter, and then write data back to external memory. This convoluted process expends packet processor cycles and is bandwidth intensive across the memory bus between the CPU and external memory. As line rates rise, the number of statistics operations and usage of the memory bus may starve the processor cores of context or data, causing the processor to stall and line-card performance to suffer.

Network equipment designers attempted to address the problem by offloading all or parts of the statistics task from the core packet processor. Some designers moved the statistics function to dedicated logic in an FPGA, for example, or integrated it into an ASIC. Both of these solutions present major liabilities, however. FPGAs do not offer the on-chip memory densities that high-speed statistics operations require at today's line rates. Accordingly, designers must support the FPGA with an external SRAM and face the same read/modify/write latencies associated with traditional addressing and SRAM configurations. Dedicated ASICs offer higher performance and the ability to add larger quantities of memory on-chip. But with average ASIC NREs exceeding a million dollars, the task of designing, verifying and validating an ASIC dedicated to statistics calculations remains prohibitively expensive.

The questions facing network equipment designers become: how can the problem be solved in a cost-effective manner , how can the core packet processor, whether an NPU, ASIC or FPGA, be freed up and allowed to focus on the packet classification functions it was originally designed to address? Ideally, the solution is comprised of a low-cost, off-the-shelf co-processor optimized for this specific function and designed to eliminate the stalling issues outlined above. A solution is also required that offers a high-performance, industry-standard interface that will simplify line-card design and support the growing array of NPUs and dedicated packet processors currently in use. Finally, any solution should be highly software configurable to support widely divergent application needs.

Session border controllers One way to illustrate how a statistics engine can help address the offloading of statistics operations is to examine how it can be implemented in a session border controller (SBC). Riding the rising tide of VoIP deployment, SBCs play a key role in these networks by controlling real-time session traffic at the signaling, call-control and packet layers, as data crosses the border between networks or network segments. These devices typically sit between a trusted private network, such as a private corporate LAN, and an untrusted public network such as the Internet, or between two service provider networks. They provide access to VoIP signaling messages to the core of the network and, by controlling access of media packets to the network, support differentiated services such as billing and QoS for different media streams. Designed to secure the borders of a network, SBCs play a crucial role in the traversing of firewalls between networks and help apply such regulatory mandates as lawful interception of packetized voice.

With the adoption of Power over Ethernet, there is a change in the way we think about powering network components. At the same time, new network applications and devices are adapting to and greatly benefiting from such technology. With the combination of this standard, it is now convenient, easy to manage and cost-effective to reliably power network devices such as IP phones, wireless access points and IP-based security devices.

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