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<p>• Create a coverage model for both hardware and software.</p>

Dual-mode devices will undoubtedly attract a lot of interest because they will be capable of operating in either standard Bluetooth mode or ULP mode. Interestingly, however, the power consumption of a dual mode chip is expected to be about 80% of that of standard Bluetooth.

The dual-mode chip's power performance is lacking mostly because of Bluetooth's complicated but robust modulation scheme, which requires it to hop around in the spectrum. This makes it difficult for the device to go to sleep because it could not follow the hopping. It needs to remain in a semi-aware state at all times.

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Hence, higher power consumption. But the Wibree Forum (now subsumed by the Bluetooth SIG) estimated that the dual-mode chip will cost only about 10 cents more than a standard Bluetooth chip.

Power optimization The remarkable improvement in power optimization in the ULP chip is due to the method that ULP (and Wibree before it) uses to optimize power consumption.

A good deal of clever design including a lightweight Link Layer (LL) in the protocol stack optimized for low duty cycle applications went into ULP's inherited Wibree specification, which was, in turn, largely influenced by the technology expertise of Nordic Semiconductor.

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But the primary ULP power saving technique is most likely shutting down the chip when it is not in use, according to Paul Williamson of Cambridge Consultants. The ULP chip's radio wakes up” when it has data to transmit and the transmission itself is short.

This leads to some coexistence issues with standard Bluetooth. Since both modes use the same radio, some accommodation must be made for sharing it. Two elements in the dual-mode protocol stack—Admission Control and the DuMo Manager—have been added to avoid coexistence issue.

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A comprehensive view of the protocol stack including standard Bluetooth, ULP and dual-mode is shown in Figure 1.

Click here for Figure 1

Transport stream input The TS input block takes TS input on a number of TS ports and converts this data into frames suitable for use by the RTP transmitter. These frames are 32-bit little-endian packed versions of the TS data. Each TS port has its own clock; the TS input block retimes the TS data onto its local system clock. The TS input block is an open source Verilog HDL example that can be modified to adapt to other video input formats.

Up to 256 separate TS ports may be implemented with each port able to support up to 256 separate channels. The design consists of a number of input buffers and an output FIFO buffer. One input buffer is required for each TS input and is responsible for conversion of TS data on its associated port into frames suitable for use by the RTP transmitter. Each input buffer pushes pointers to its completed frames into the output FIFO buffer. A state machine arbitrates between the various buffers to control FIFO pushes. Items are popped from the FIFO buffer one by one, causing requests to the corresponding buffer to drive the output. Control of the output port is multiplexed between the buffers based on the request signals.

RTP to TS interface The RTP-to-TS block generates a TS output from received RTP packets. This is the reverse of the TS input block. It connects directly to the RTP receiver. The RTP-to-TS block is an open source Verilog HDL example design and also can be modified to suit any video format requirement.

Conclusion Video over IP is one of the emerging video distribution networks beside cable, terrestrial, and satellite. Utilizing low cost FPGAs, an industry open standard for error correction algorithms, and available reference designs can efficiently assist system integrators and designers to development a flexible, cost-effective video network that can handle signal degradation.

About the author Tam Do is the senior technical marketing manager of the Broadcast/Consumer Applications Business Unit of Altera Corporation. He is responsible for all technical and marketing issues related to the digital broadcast, automotive, and consumer electronics industries. Mr. Do joined Altera in June 2003. Before that time, he was most recently the application design manager of LSI Logic's Consumer Product Group, where he focused on the development design of an ASSP evaluation system and software for the set-top box industry. Mr. Do holds a BSEE from the University of Nevada Reno, and has close to 20 years of electronics system experience with LSI Logic, Stratex Network, and Verizon Corporation. He can be reached at

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TVP9900 Evaluation Module To help designers evaluate the TVP9900 demodulator and test design concepts quickly, TI supplies the TVP9900 EVM. This printed circuit board provides circuitry, along with test points and jumpers, for operating the TVP9900 and dynamically troubleshooting the chip's functions within a receiver system. The WinVCC software included with the EVM provides one-click settings for 8-VSM and 64/256 QAM demodulation.

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