<p>About the Author <i>William Ruh , as vice president of technology architecture in Cisco Services, has worldwide responsibility for the strategy, direction, coordination, and delivery of all AON- and SONA-related services. Bill brings more than 20 years of industry experience and expertise in enterprise middleware and integration technology. Prior to joining Cisco, Bill was the CTO and senior vice president at Software AG, Inc. Bill is also a noted author and has served in executive capacities at several entrepreneurial companies, including The Advisory Board and Concept Five Technologies.</i></p>

Code shells for SCA components can be generated in OWD, effectively reducing the development time a programmer spends on SCA overhead (that is, code which is not directly related to the component's primary purpose). OWD provides the user with a graphical user interface for adding ports and properties to a component shell. When the component shell code is generated, the appropriate code for the desired port structure used to interface with other components and for the specified reconfigurable properties is appropriately incorporated. As OWD improves, additional features are added to the component generation and full SCA compliance is gradually approached. Refer to the section on Component Development for more information on the component editor.

EE Times: What are your greatest challenges with respect to functional verification?

Moshar: All of our products have an enormous amount of man-machine analog interface content, including audiovisual, voice and telephony. We have high-level signal-processing and communications algorithms. And an enormous amount of embedded processing takes place in these chips, so layers of software need to be managed.

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Because the entire system is on a chip, there is no target environment for it. That lack of a target, that lack of a representation you can build a testbench for, makes it very difficult. It takes away some of the advantages an in-circuit emulation environment can provide. Also, because the life cycles of our products are short and the intellectual property [IP] that's integrated into them changes, we can never enjoy the concept of golden IP. Everything has to be reverified as we go.

EE Times: How would you describe your verification setup?

Moshar: At a high level, it is comprised of a C/C++ object-oriented testbench. It's entirely transaction-based, and it can connect to a hardware representation of the device under test or a software representation of the device under test seamlessly. One key attribute is that the system testbench is untimed, and the way it interacts with the simulator or the hardware accelerator is untimed. But it is 100 percent in control. This is the infrastructure we put in place more than a decade ago.

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We can think of the high-level testbench environment as a superset of what [Cadence Design Systems'] Specman does today. Specman allows you to create various traffic scenarios at the clock level or transaction level to cover corner cases. Our environment does basically the same thing [but] at a much higher level of traffic. A high-level simulation engine running C/C++ takes care of all the scheduling, traffic generation, monitoring, determination of the time, extraction of the data and sorting of errors. It is a very elaborate environment.

EE Times: You've called this methodology co-modeling. How does it compare with co-simulation?

S7D20.000000A20F30T_Datasheet PDF

Moshar: Co-simulation means the software simulator is running on the workstation, and through a PLI [programming language interface] you're talking to a device or bus-functional model that is working in conjunction with the simulator. Co-modeling is the other way around. A C/C++ testbench is in control, and it communicates to a simulator or a hardware box via a well-defined set of APIs with transactors.

EE Times: You've recently made a major investment in hardware acceleration. Why?

How these phases work together is illustrated in Figure 3 . In the case of Posted Write, the Request Phase” comes first where Master issues a command to the Slave. The Data Handshake Phase” follows. The Master transfers the write data to the Slave independently of the requests.

In the case of NonPostedWrite , the Response phase” is added to the Posted Write case. The Response phase” initiates a response from the Slave when the write is finished.In the case of Read”, where the read data is transferred, the response phase follows the request phase. This is the mechanism which executes the Split Transaction”.

OCP defines the signals of the three Phases. From the signals defined by OCP, the critical signals of clock and reset commands are chosen. And then signals such as address, write data path, read data path, burst signal and flow control signal are chosen when needed.


Network protocol stack The network protocol stack is an implementation of well-known network protocols like TCP, UDP and IP. The network protocol stack can be provided as a configuration module of various operating systems, as discussed earlier.

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