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Fig 2: SH7724 block diagram – an architecture borrowed from the mobile phone baseband.

How is IMEC going to pay back $50 million?

Scaling methods apply to EUV, says IMEC litho chief

06035A101KBT1A_Datasheet PDF

LONDON — STMicroelectronics has produced the first prototypes of the Morpheus chip, produced under the Morpheus collaborative research program which has been running for several years.

The Morpheus IC contains 97 million transistors and is expected to consume no more than one watt of power while including a reconfigurable instruction set architecture processor and programmable logic fabric provided by M2000 SA, the predecessor to Abound Logic Inc. (Santa Clara, Calif.).

The EU-funded project includes big manufacturers of embedded systems such as Thales, Thomson, and Alcatel-Lucent.

06035A101KBT1A_Datasheet PDF

Philippe Bonnot of Thales Research and Technology, project co-ordinator, points out that the silicon technology used in the chip is several years old. We only used 90 nanometre technology,” he said. So with more aggressive technology we could get some better results — we could put more units on to the chip and we could have a higher clock frequency.”

Bonnot said he expects there will be several modifications to the prototype before it can be considered for commercialization. In the meantime, the SMEs in the project may be able to market one of the reconfigurable units and a compiler.

06035A101KBT1A_Datasheet PDF

The Morpheus chip will be integrated into several application boards for testing by the larger industrial partners. Video and network applications will be a priority. It will be interesting to see if this new approach can really attract the interest of our companies,” Bonnot said.

We tried to solve all these problems by merging a processor with reconfigurable units embedded in the same component,” says Bonnot. Reconfigurable hardware can be programmed to connect itself in many different ways. When a new application is required, the hardware can be modified just as a piece of software can be altered to do a different job.

Therefore, adding memory to the mix, is the SH7264/2, due to be launched in October 2009 implemented in 65-nm. It combines an SH-2A core with 1-Mbyte of SRAM together with a video engine for GUIs and USB and CAN connectivity. The SH7264 comes in a 176-pin package while the SH7262 in a 208-pin package.

The SH7724 – see figure 2 – is also due to be launched in the third quarter of 2009. This is a complex chip with an architecture borrowed from the mobile phone baseband. The SH-4A core while being highly capable, is predominantly a housekeeper for hardware accelerated graphics, camera and connectivity functions.

Fig 2: SH7724 block diagram – an architecture borrowed from the mobile phone baseband.

To see a bigger version of this graphic click here.

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