Laird Connectivity

<p>Completing the package, Oppo Digital includes a 49-button remote with 'glow-in-the-dark' navigation, menu, keypad, and setup keys. It was relatively ease to use. Although, I have to say that always seemed to hit the 'Stop,' button instead of the 'Pause' key, which is right next to it. The 'Stop' key is centrally-located just below the large round navigation button, and the 'Play/Pause' is located to the left of the 'Stop' key. A minor quibble as I would have liked to see the 'Play' button directly below the navigation keys.</p>

FPGA plus discrete ADCs/DACs A complete color space converter system can be constructed from a digital FPGA, three discrete high-speed, 10-bit ADCs, and three discrete high-speed, 10-bit DACs. This is a straight-forward, albeit expensive, approach. It benefits from no upfront NRE charges and can be implemented quickly. On the other hand, using an FPGA plus six discrete high-performance mixed-signal devices is very expensive. These seven components plus support circuitry consume a considerable amount of PCB board space and require extra manufacturing steps that result in high manufacturing costs and reduced reliability. The high-speed parallel buses between the ADCs and DACs also increase the pin-count requirement for the FPGA which further raises the overall solution cost. Furthermore, the increased I/O drive causes the already power-hungry FPGA to suffer from increased power consumption. This solution is adequate for very low volume products where power consumption is not a major concern.

Table 2. HSDPA categories [1]

Maximum data rate (referenced to different HSDPA categories) is determined by modulation scheme and code rate (TFRC: Transport Format and Resource Combination) as well as number of codes used.


CMOS As preferred UMTS transceiver process Although multi-band capability and HSDPA support are clear transceiver trends targeted by all transceiver vendors, a no-way-less-important trend is the emergence of CMOS (Complementary Metal Oxide Semiconductor) technology, which is becoming a technology of choice for transceiver design implementation, replacing the SiGe (silicon germanium) and BiCMOS (bipolar CMOS) processes. Almost all of the leading transceiver vendors are now using CMOS in their current designs.

CMOS offers a direct cost advantage over such traditional RF technologies as BiCMOS and SiGe because it requires fewer masks and processing steps. CMOS technology features faster transistors and low size area, resulting in a very small design footprint. Such cost reductions, along with enhanced integration possibilities, are among the forces driving the move of next-generation RF designs to CMOS.

As exemplified by the Infineon SMARTi 3G transceiver, CMOS allows for a high overall percentage of digital logic to be implemented. This leads to flexibility in integration of various compensation techniques, such as DC offset and filter calibration, and also makes possible such features as a short locking time and fast frequency settling for the fractional-N PLL. Some specific features, such as RAM readback that allows keeping the pre-programmed register settings in a special RAM in a sleep mode so that the IC remembers them at next wake-up, are only and exclusively possible with a CMOS process.


Because CMOS is used by semiconductor manufacturers in many other products, the same generic technology process and production line are generally available for monolithic integration of the digital, RF and mixed-signal elements of a mobile phone on the same die, leading to even smaller sizes and a much higher integration level.

According to research firm iSuppli Corp., RF CMOS technology will enjoy increasing growth over the next few years, reaching around 40 percent of the market share by 2009 [2].


Conclusion The need for an increasing number of multi-band handsets is driving the demand for high-performance, cost-competitive RF transceivers that are capable of supporting different frequency bands. A truly multi-band single-chip transceiver, such as Infineon's SMARTi 3G, provides designers full flexibility in developing multiple mobile handset solutions from the same RF platform design. Due to the high re-use factor, systems based on such a transceiver can be easily adapted to the various band-combination needs of future mobile applications with a minimum of software and hardware effort. Full compliance with HSDPA requirements for higher data rates gives system designers an easy migration path to next-generation UMTS handsets based on the same architecture, further saving costs and design time.

References [1] 3GPP TS25.306, UE Radio Access Capabilities Definition,” version 5.8.0.(

Over the last eight years there has been a 30× increase in logic density and memory bits in FPGA devices. The largest FPGAs – such as the recently announced Stratix III EP3SL340 from Altera – contain up to 338,000 equivalent logic elements (LEs) and more than 17 Mbits of embedded memory.

This rapid increase in logic density translates to an even larger increase in computing requirements for design compilation and place and route. Unfortunately, CPU speed has only increased by a factor of 11× during the same period. With FPGA design complexity outpacing CPU speed, FPGA designers are more dependent on design tools and methodologies that speed compile times and allow them to iteratively and efficiently debug, add features, and close timing. This article presents a three-stage methodology to increase productivity for engineers designing with high-end FPGAs.

Three-stage solution to reducing compile time Compile times can be substantially reduced by utilizing a combination of place-and-route algorithm improvements, use of the latest computer technology, and instituting best practice design methodology.

Place-and-route algorithm improvements Place and route algorithms for FPGAs are continually improving and delivering better results in less time. In recent years, algorithms have been enhanced to more efficiently use the memory and bus speeds available in workstations. Memory consumption is a challenge as FPGAs continue to scale in size. Successfully managing memory use yields many benefits including cheaper machines, the ability to use a 32-bit operating system, better cache locality and hence run-time. As algorithms are tuned to more efficiently target a specific FPGA family, compile times are significantly reduced (i.e. a 47% reduction in compile times has been realized since the initial introduction of Stratix II using Quartus II software).

Computer technology While CPU speeds have not matched the increase in FPGA device densities, a change in computer architectures can provide a performance boost. Multi-core CPUs are now becoming mainstream in computer workstations. A new generation of processors supports dual processors on a single chip and motherboards support two or more processors on a single board.

Copyright © 苏ICP备11090050号-1 tl431 datasheet All Rights Reserved. 版权投诉及建议邮箱