Fremont Micro Devices

<p>Industry observers termed the decision a victory for inventors because it effectively prevents patent holders from using their monopoly to close off entire areas of technology innovation. Critics have argued that some software patents have blunted innovation in that field.</p>

Swanson: I think what's going on is really more of the same if you get through the smoke in the room. Communications was an area where we were all waving our hands to make sure Wall Street knew we were all very much involved. We're a diversified company, and we didn't get clobbered as hard as some other people, and there's still all kinds of stuff going on in the computer business, the communications business-whether it's cell phones or optical networks. Cisco's [recent optimistic forecast] gave a lot of people hope that the world didn't come to an end, that you just had this huge amplitude created by some of the supply-based management problems.

Timing closure is not simple to achieve. And the solution needs to be robust, yet easy-to-use and accessible to the FPGA designer. ASICs and FPGAs require different implementation strategies, yet both have many things in common. Both use leading-edge technologies, currently 0.13 micron. Both are typically designed with VHDL or Verilog. Both are not shipped until timing is achieved. And finally, both have the ever-increasing challenge of timing closure for designers.

Many EDA vendors are trying to solve the challenge of achieving timing closure in a deep-submicron ASIC. The migration of ASIC designers to FPGAs and the advancements in FPGA architectures are also causing FPGA tool vendors to look seriously at this same challenge. The timing closure challenge in FPGAs is driven by the increase in complexity and performance of the current generation of FPGA devices. Ensuring that performance is achieved with these complex devices-which contain advanced building blocks such as DSP structures, high-speed I/O interfaces, specialized memories and built-in processors-requires a new approach to FPGA synthesis, one aimed specifically at achieving timing closure. The biggest challenge to timing closure is the gap between the physical and logical worlds. For performance reasons, the current generation of synthesis algorithms estimates interconnect delay with wire-load models based on fan-out. With the previous generation of programmable devices and designs, this approach was sufficient because the gate delay accounted for the majority of the delay. With the new generation of devices, this is all changing. In these new larger and faster devices, interconnect delay can account for up to 70 percent of the total delay. To achieve the best synthesis results, interconnect delay must be accurately modeled; hence the concept of physical synthesis. To make physical synthesis efficient, the synthesis database must seamlessly contain both the logical and physical data.

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The term physical synthesis has market appeal. It covers anything remotely connected with using

physical data to improve synthesis results. The term means different things to different people and companies. It is helpful to remember that synthesis is a generic term that spans the synthesis or conversion of register-transfer level (RTL) to logic and the optimization of that logic. In its most generic form, physical synthesis combines placement with synthesis algorithms to produce a better quality of results (QoR). This can be achieved in two general areas.

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The second area grouped under the physical synthesis banner can also be referred to as physical optimization. The focus is to use physical data to improve the optimization routines. Today's FPGA physical synthesis tools fit mostly under physical optimization. This will change as complexity continues to increase and designers move from floor planning to design planning.

Two constants characterize timing closure: the challenge varies from design to design, and designers want to get their product to market quickly with the least amount of work.

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To address how timing closure problems can vary between designs and time-to-market pressures, the tool must provide a number of alternative solutions. It is important that the solution first takes an automated approach. However, for the extremely difficult timing closure problems, designers must be able to interact with the tool and their designs in both the logical and physical worlds to achieve timing closure and ship their parts.

FPGA designers have long achieved timing closure even before EDA vendors started making noise about physical synthesis. Common approaches include rewriting the RTL, design iterations, working with the timing constraints and grouping cells. These approaches worked in most cases because the overall delay was driven by the cell delay and not by the interconnect delay.

Power supply vs. modem Higher power supply switching frequencies have less of an effect on the overall data rate, for two reasons. The first is that higher switching frequencies affect higher-frequency bins, which have lower bit rates to start with. The second is that the harmonics are spaced farther apart, so fewer bins are affected.

Power supply switching frequencies greater than 1.1 MHz typically have a minimal or no impact on the modem data rate, since the fundamental of the switching frequency is higher than the frequencies used to transmit data. Reducing the switching frequency below 100 kHz will move the fundamental below the first downstream carrier band, but the harmonics will affect many carrier bands up to 1.1 MHz.

Other frequency effects Based on throughput only, a power supply switching frequency of greater than 1 MHz is obviously desirable from an interference standpoint. But there are other power supply factors that are affected by the switching frequency. They include the supply's overall volume, cost, efficiency and reliability. None of those factors can be optimized independently of the others, and in many cases, optimizing only one supply parameter leads to a less-than-optimal overall solution.

Increasing the switching frequency of an ADSL power supply reduces the volume for two reasons: smaller passives and higher allowable ripple. Figure 2 shows that lower switching frequencies require a lower output ripple to maintain a data rate of 6.7 Mbits/s. For example, at 100 kHz, the allowable ripple for 6.7 Mbits/s is 10 mVpp, while at 1 MHz, the allowable ripple is 80 mVpp.

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Meanwhile, Japanese LCD suppliers, which have lost market share to Korea- and Taiwan-based suppliers, continue to revise their strategies.

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