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<p>Can You Come Home Again?</p>

ASSP med FPGA Ett sätt att göra ASSP-kretsar mera flexibla är att kombinera dem med (små) block av programmerbar logik. Hittills har flera försökt, men få lyckats. Ett företag som har förutsättningar att lyckas IBM. De har ett avtal med Xilinx som tillåter dem att använda deras FPGA-teknik i block för ASIC eller ASSP-lösningar.

Based on the complexity of the problem, it is not difficult to understand why today's standard of static IR-drop for final verification is insufficient to handle the power integrity problems facing designers using 150nm and smaller geometries. What is required is a new physical power flow, which has the ability to address these issues and assure full-chip power integrity.

3. The new physical power flow

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In the traditional physical design flow, static IR drop analyses are performed close to tape-out, when all physical design information is available. As mentioned earlier, these analyses do not capture and identify important power integrity issues in a design. Dynamic power grid analyses provide the missing link in the backend verification flow. However, even greater benefit can be obtained by avoiding these issues early in the design flow, starting with power grid planning.

Power grid planning Power grid planning needs to begin early, once power estimation for macros and top-level blocks is complete. Different grid designs and grid sizes need to be explored automatically as placements become available. Static and dynamic hot spots can be identified and different grid options and decap solutions can be determined to resolve them.

Package RLC models can be considered along with on-die networks to get a realistic voltage drop picture. Different pad locations can be explored to verify their usefulness and effectiveness. Options for hooking up macros and IP to the top-level grid can be investigated.

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The power grid planning process should honor blockages and specific routing requirements. It should automatically generate grids that meet pre-defined IR drop budgets and all other design constraints. Engineers can then plan their power grid (metal usage, pad locations, and decap allocation) from the very start of the design process, alleviating power integrity issues and surprises just prior to tape-out.

The new physical power flow (see Figure 4) enables designers to plan and engineer their power grids from the start of the design cycle and to incrementally update them as more information becomes available. The key objectives are to undertake consistent power analysis from the start of the design process and to explore options for automatic grid design, grid sizing, power pad and decap placement, and so on, as the design evolves.

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As the power numbers and initial placement become available, designers can initiate power grid planning. Different options, such as power rings around macros, global mesh with different pitch and design styles, and pad placements, can be explored automatically to meet specified IR-drop targets. As the design evolves with trial routes, designers can refine the grid to meet routing and design constraints.

IR-drop analysis can be done at each stage for verification. These analyses should incorporate capabilities highlighted in the following section. After initial placements, the power grid planner will advise on decap insertion and grid sizing to resolve dynamic hot-spots. Towards the close of the design cycle as the complete design information becomes available, designers can verify the effectiveness of the grid with a full-chip dynamic verification for final sign-off.

One audience member asked whether the tapeout model is a stalking horse” for cutting costs. If you look at companies using tapeout based models, it actually comes out to be slightly more dollars per tapeout,” Tobias responded.

Another audience member noted that an EDA vendor has little control over when a customer will do a tapeout. If enough customers do enough tapeouts, statistically it works out,” Benkoski replied.

Most of the criticism, however, was leveled at the bundled tool packages offered by the big EDA vendors. We're finding that difficult to come up against, because customers can receive a specific tool for a very low cost,” said Graham Bell, senior director of marketing at Nassda.

Their [big EDA vendor] model is an all you can eat model, and they're trying to lock up the customer base,” said Thomas Heydler, Barcelona CEO. Synopsys and Cadence, their goal is to own the flow, to occupy every step in the flow. And once you've locked in the flow, why innovate?”

I don't see innovation coming from the companies advocating that [bundling] model,” said Tobias, who later referred to the brain dead and stupid business models” offered by the big EDA vendors.

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Flautner said the consumer market requires increased battery life for cellphones and new functions. Cellphones that used to have a few hours of talk and stand-by time now have four hours of talk time and of 240 hours stand-by time.

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