Harris

<p>MADISON, Wis. — An IC designers’ job is mired in what if’s.” Depending on choices among of metal stacks, process flavors, or types of memory architecture, a new design could result in a chip dramatically different in power, performance and area.</p>

Article originally posted on EE Times Europe.

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SEATTLE — The recent burst of activity in the EDA, foundry, and contract chip design industries indicates that they have joined the scramble to stake out territory in the Internet of Things (IoT) market. While the design and fabrication of ASICs has broad applicability, EDA companies are now creating platforms and developing tool packages specifically to reduce barriers to entry for IoT design teams. The result may be a new wave of custom connected devices.

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There are two major perceived issues with ASICs that have lead IoT design teams to work primarily with off-the-shelf resources instead, according to Huzefa Cutlerywala, a sr. director of Technical Solutions at custom chip designer Open-Silicon. They think of ASIC design as being something long term,” Cutlerywala said in an interview with EE Times. Because time to market is one of their main concerns, IoT designers have been avoiding ASICs.” The second major issue holding back ASIC use in the IOT, Cutlerywala pointed out, is risk. It’s much safer when you’re starting with out-of-the-box functionality.”

But ASICs have significant advantages to offer the IoT design community, Cutlerywala added. Perhaps surprisingly, the traditional ASIC cost advantage in high-volume production is not necessarily one of them. For IoT developers,” Cutlerywala said, the product differentiation, added security, and form factor control that ASICs permit are more valuable than low cost.”

Samsung was shy on specs, but said the process node will be in full production by the end of 2016, about the same time as its rival TSMC. The Samsung 10nm process offers significant power, area, and performance advantages” and targets a broad range of markets, said foundry senior vice president Hong Hao.

This is one of the biggest positive steps for the industry in the last few years. It shows that Samsung sets these very aggressive goals, and they may not hit them exactly but they will be very close,” International Business Strategies CEO Handel Jones told EE Times. If they can achieve 10nm, that will be hugely disruptive.”

Apple will play a large role in determining the 10nm leader because of its massive wafer volumes, Jones said. The company orders 40,000 wafers per month, which would significantly help fill a fab but also require $8 billion in capital expenditures from a chip maker.

Samsung is expected to make Apple’s iPhone 7 SoC in its 14nm process, in large part because it beat TSMC to market by several months. Jones said Samsung has a high probability of getting Apple’s 2016 and 2017 business in 10nm, which will be followed by business from second-largest volume purchaser Qualcomm.

The only customer that will really drive [high wafer volumes] is Apple. If you miss the big ones then you basically have a big problem,” Jones added.

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