Signal Transformers

<p><i>NICOLE LEWIS is a freelance writer and former senior editor at Electronic Buyers News.</i></p>

The initiative plans to establish a nonprofit company in the U.K. by the end of July that would develop an integrated network for fourth-generation mobile phones, enabling operators to provide network services. It is targeting 2010 for delivering commercial services.

IC designers, Tay said, go through a lot of trial-and-error work to determine interconnect loads and worst- case corners for delay times. Our product saves all this tedious work, which means we can shorten the design cycle, quickly calculate the interconnect load, and give [designers] estimated worst-case delays and crosstalk in a very accurate manner,” Tay said.

Nanno Solutions sees itself as a DFM company, Tay said, because it takes actual process variation data and transforms it into realistic values for engineers. As such, he said, the company's tools help designers improve both performance and yield. He noted that the company is focusing on both parametric and process yields.

transistors integrated circuits

Nanno Solutions was founded by Tay and by Won-Young Jung, CTO, in 2004.

There are several methods for generating worst-case interconnect models today, said Tay, but all are lacking. Conventional calculation is too conservative and not realistic. The Monte Carlo method is precise, but too time-consuming.

Nanno Solutions has developed a new methodology, called maximum probability,” that claims to accurately and efficiently predict non-normal distributions. The approach claims to be two times faster than Monte Carlo analysis alone, with a maximum relative error under 4.5 percent for worst-case and 0.6 percent for best-case compared to measurement.

transistors integrated circuits

The company said that worst-case corners calculated with Monte Carlo analysis generate only numerical values, not realistic worst-case corner values. This dilemma can be solved, it said, by selecting a value that has maximum probability” as worst case for a given range.

Input to Nanno-Win, Tay said, is a process technology file that includes a description of the interconnect structure, options such as dimensions and temperature, and control-related parameters such as simulation range. The company's tool can be used with third-party extraction tools for back-end design, or coupled with Nanno-Cal for front-end design.

transistors integrated circuits

Nanno-Cal takes in the Nanno-Win models and outputs a Spice-compatible netlist. Nanno-Cal estimates interconnect loads and calculates delays and transient times. It also estimates crosstalk and IR drop for selected nets prior to layout.

Nanno-Win and Nanno-Cal are available now for $150,000 and $40,000, respectively.

Meanwhile, CNSE scientists and engineers will work with their colleagues from Vanderbilt University's Institute for Space and Defense Electronics (ISDE) to develop a computer chip to improve radiation hardness through process innovations, as part of a project sponsored by the U.S. Office of Naval Research.

A team of researchers from CNSE, Vanderbilt and several industry and government partners will begin collaboration on 90-nm and 65-nm computer chip device technologies and work to develop future nanotechnologies at sub-45-nm node.


July 15, 2006

Earnings rush

Magma's been hitting the discount rack

Copyright © 苏ICP备11090050号-1 tl431 datasheet All Rights Reserved. 版权投诉及建议邮箱