IQD Frequency Products

<p>Intel Corp., for its part, wants extreme-ultraviolet lithography to be ready by 2007 for development of the 32-nm semiconductor node, expected to go into production at the end of the decade. Technically, EUV can be used for most of the post-2010 period, and no other approach offers the same extendability, said Peter Silverman, director of lithography capital equipment at Intel.</p>

If 157 loses the battle to 193-immersion, then in my opinion it is optimistic to believe that for the 32-nm [chip-manufacturing] node the industry will solve all of the 157-nm problems, including the pellicle, the resists and the quality of the calcium fluoride crystal, and then on top of that find a liquid that works with 157-immersion,” he said.

Architecturally the design is aggressive, but not out of the mainstream. A 32-bit scalar RISC processor is paired on a high-speed bus with a bank of four 16-bit vector processors that support both conventional and chained vector operations from 32-element vector registers.

With all that horsepower, the potential throughput of the TVP400 is enormous. Consequently, so is its demand on memory bandwidth. Founder Howard Sachs estimates the peak memory bandwidth demand of the processing units at 38.4 Gbytes/second. The only way to support this appetite is to embed large memory structures next to the processing units.

RN60D3402FRSL_Vishay Dale_Through Hole Resistors

That is where the Telairity methodology really comes into its own, Sachs said. A conventional ASIC methodology would couple synthesized logic with compiled memories to produce the processor core. But Telairity feeds its CPU with 600-MHz caches, and its vector units with a combination of a 12-port SRAM and a crossbar switch, also operating at 600 MHz. Those memory structures are beyond the range of memory compiler techniques.

By constructing the TVP400 hard macro from its retargetable block library, Telairity can offer a piece of approximately 600-MHz IP that can be fabricated in a range of 130-nm logic processes. The company is estimating that the performance will be 600 MHz at 85 degrees C, dropping to 440 MHz at the slow/slow process corner. In the presence of large process variations, a conservative design could drop back to 400 MHz, Sachs suggested, leaving enough headroom to all but obviate signal integrity issues.

At this speed, and with the level of concurrency the core provides, the device should be able to handle a number of applications-such as HDTV set-top boxes-that are beyond the range of any signal-processing IP available today, Sachs maintained. It is an offering made possible by a novel design methodology enabling very fast multiport memories and fast data paths.

RN60D3402FRSL_Vishay Dale_Through Hole Resistors

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RN60D3402FRSL_Vishay Dale_Through Hole Resistors

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FPGA designers today are looking for complete integrated design environments to help accelerate their time-to-market,” said Tom Feist, director of product marketing, FPGA Synthesis, Mentor Graphics. By partnering with Actel, we are meeting this requirement by offering our mutual customers Mentor's industry-leading point tools such as ModelSim, LeonardoSpectrum, and Precision Synthesis, integrated within the Libero design environment, as well as offering Actel's Designer v5.0 within our own integrated environment, FPGA Advantage.”

SynaptiCAD has continued its partnership with Actel to provide best-in-class EDA tools for designers of Actel's FPGAs,” said Dan Notestein, president of SynaptiCAD. The easy-to-use WaveFormer Lite testbench generation system fits seamlessly into the Actel Libero IDE and allows designers to meet their time-to-market goals when designing current and next-generation FPGAs.”

The Actel Designer v5.0 software contains several ease-of-use enhancements, including ChipPlanner and the Multi-View Navigator. A comprehensive graphical interface for user-driven device floorplanning, ChipPlanner enables designers to achieve the best tradeoffs between optimal design density and performance through the management of regions, logic placement, I/O assignment, and routing. The new Multi-View Navigator simultaneously displays ChipPlanner, Netlist, Package, I/O Attributes, Hierarchy, and Log Window views, thereby offering designers a comprehensive and efficient design-management methodology. Further, improvements to the Placer and Router functions in Designer v5.0 provide up to 15 percent additional performance improvements for Actel FPGAs.

About the Libero Integrated Design Environment

Actel's Libero comprehensive design environment integrates industry-leading design tools and streamlines the design flow, manages all design and report files, and seamlessly passes necessary design data between tools. The Libero tool suite supports mixed-mode design entry input, giving designers the choice of mixing either high-level VHDL or Verilog HDL language blocks with schematic modules within a design.

Three architectures

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