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<p>Apart from those differences, the models are identical. Each comes with a 400-MHz AMD K6-III+ processor and 32 Mbits of DRAM, and uses a PCI bus for PC-based platforms. Both drop in” to replace other a-Series boards. They improve sampling period resolution to 50 ns and offer low latency-0.1 ms task time quantum-for fast response.</p>

Claim – The ornamental design for a nose pick as shown and described.

Jim McGregor TIRIAS Research, Founder/Principal Analyst jim@tiriasresearch.com

NEW YORK — After nearly two years in the works, Intel Corp. and Analog Devices Inc. here today finally announced its long-awaited digital signal processor (DSP) architecture.

QTE-060-01-F-D-K-TR_Datasheet PDF

The codenamed Frio DSP, co-developed by both Intel and ADI, is being formally called the Micro Signal Architecture (MSA).” The modular core itself is a fixed-point, 16-bit architecture that will initially run at speeds up to 300-MHz, said Ron Smith, vice president of the Wireless Communications & Computer Group at Intel.

In the future, the core will be optimized to run at speeds of 1-GHz, Smith said. We call our device the Micro Signal Architecture, because it combines signal processing and the simplicity of microcontrollers,” Smith said at a press event today.

The chip will have more than six times the performance than competitive products on the market, Smith said. Running at 336 million instructions per second, the device also features power-management and multimedia instruction sets.

QTE-060-01-F-D-K-TR_Datasheet PDF

At this event, the companies only announced the DSP architecture–not the merchant chips themselves. Both Intel and ADI will take this MSA-based core and develop separate chips based on this architecture, added Jerry Fishman, CEO of ADI.

In other words, Intel and ADI will develop their own DSP chips, which will not be pin-compatible, the companies said. First products are expected to hit the market from the respective companies in 2001.

QTE-060-01-F-D-K-TR_Datasheet PDF

This is the next-generation architecture for ADI's DSP business,” Fishman said at the event.

Intel, on the other hand, will not go after the general-purpose DSP market, Smith said. We are going to use the DSP as an embedded part rather than a general-purpose DSP,” he said. Our focus is targeted at vertical applications like wireless handsets,” he added.

Other techniques for extending” PCI include a PLX proposal that bridges multiple PCI buses together using the so-called Sebring ring technology. The problem here is that this is PLX proprietary technology and thus unlikely to become a widespread standard. Also, since it's based on a ring technology, it scales up only to the size of the ring, after which you have to build multiple rings.

Also on the horizon for extending PCI is a very interesting technology from StarGen – a PCI bridging technology that runs on high-speed switched serial interconnects. Though based on a high-speed switched protocol rather like Infiniband, it has an advantage of supporting native PCI-to-PCI bridging. StarGen plans to make their high speed serial protocol generally available and it's compatible with current industry open standards for interconnects. But the most interesting feature is its PCI-to-PCI bridging. This means it can work with current PCI software. While it's not shipping yet, this technology is worth tracking.

Beyond H.110. Although it doesn't give a great deal more capacity, one idea is to just double the clock speed on the current H.110 bus. Unfortunately, simulations show that to make the bus actually work across all 20 slots on a full-sized backplane, clock speeds must remain where they are today. At too high a frequency, electrical signals from one bus segment will never reach another, as they will radiate away from the bus as they would from a radio or TV antenna.

So if you want to speed up the H.110 CT Bus, you can only do it with substantially shorter bus segments. And, in the end, you'd only get a factor of two in improvement, whereas engineers and customers are looking for a factor of five or even ten. Mitel has designed an H.110 interface chip that could operate at the higher speed, but no one has proposed trying to standardize this.

Interestingly, the StarGen switch fabric mentioned above is also going to be available as an expansion path for H.110. This comes about through an agreement between Lucent MicroElectronics and StarGen whereby Lucent is going to build a successor to its widely adopted Ambassador Series chip. This will provide bridging between separate H.110 bus segments, with full switching, using the StarFabric to interconnect H.110 bus segments. This means you could make multiple short segments of H.110 within a chassis and switch between these segments over the bridges through the StarGen fabric.

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And yet, Penzias said, Each one of these three problems is being solved today,” and he predicted that within the near future, wherever you are, you'll be able to have a reliable machine getting you all the data you want.” At that point, said Penzias, the bottleneck shifts. Then the problem becomes how you get that data into your brain so you can make a decision.”

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