Amphenol Wilcoxon Sensing Technologies

<p>Whereas Cartier was able to turn around his prototype quickly, Dick Tracy's watch has proved more elusive. But its allure as an intellectual exercise persists, especially among engineers with childhood memories of the comic strip.</p>

This cost reduction and easy of use has been a great leveller and has made the traditional 8/16/32-bit distinction irrelevant. At the same time the number of competing 32-bit architectures has dramatically shrunk. In 1992 there were some eleven different architectures, today there are four. This is likely to shrink even further, probably down to two.

A simple 3-bit capacitor DAC is shown in Figure 3-4. The switches are shown in the track , or sample mode where the analog input voltage, AIN , is constantly charging and discharging the parallel combination of all the capacitors. The hold mode is initiated by opening SIN , leaving the sampled analog input voltage on the capacitor array. Switch SC is then opened, allowing the voltage at node A to move as the bit switches are manipulated. If S1, S2, S3, and S4 are all connected to ground, a voltage equal to –AIN appears at node A. Connecting S1 to VREF adds a voltage equal to VREF /2 to –AIN . The comparator then makes the MSB bit decision, and the SAR either leaves S1 connected to VREF or connects it to ground, depending on the comparator output (which is high or low depending on whether the voltage at node A is negative or positive, respectively). A similar process is followed for the remaining two bits. At the end of the conversion interval, S1, S2, S3, S4, and SIN are connected to AIN , SC is connected to ground, and the converter is ready for another cycle.

84535-101_Datasheet PDF

Note that the extra LSB capacitor (C/4 in the case of the 3-bit DAC) is required to make the total value of the capacitor array equal to 2C so that binary division is accomplished when the individual bit capacitors are manipulated.

The operation of the capacitor DAC (cap DAC) is similar to an R/2R resistive DAC. When a particular bit capacitor is switched to VREF , the voltage divider created by the bit capacitor and the total array capacitance (2C) adds a voltage to node A equal to the weight of that bit. When the bit capacitor is switched to ground, the same voltage is subtracted from node A.

Because of their popularity, successive-approximation ADCs are available in a wide variety of resolutions, sampling rates, input and output options, package styles, and costs. It would be impossible to attempt to list all types, but Figure 3-5 shows a number of recent Analog Devices' SAR ADCs that are representative. Note that many devices are complete data acquisition systems with input multiplexers that allow a single ADC core to process multiple analog channels.

84535-101_Datasheet PDF

While there are some variations, the fundamental timing of most SAR ADCs is similar and relatively straightforward (see Figure 3-6). The conversion process is initiated by asserting a CONVERT START signal. The

84535-101_Datasheet PDF

It should also be noted that some SAR ADCs require an external high frequency clock in addition to the CONVERT START command. In most cases, there is no need to synchronize the two. The frequency of the external clock, if required, generally falls in the range of 1 MHz to 30 MHz, depending on the conversion time and resolution of the ADC. Other SAR ADCs have an internal oscillator that is used to perform the conversions and require only the CONVERT START command. Because of their architecture, SAR ADCs allow single-shot conversion at any repetition rate from dc to the converter's maximum conversion rate.

Amplifier output noise: = 1.8 nV/rtHz * 20 V/V* SQRT(600 MHz) = 881 uV NoiseADC noise floor: 71.3dBFS at 1V Full Scale = 272 uV

In this case, the amplifier will contribute far more noise than the ADC. A WCDMA receiver has 5 MHz of signal bandwidth per channel. In order to have a flat response over 5 MHz a 25 MHz filter will be used. In order to have good filter rejection we will select an IF frequency of 185 MHz (in the third Nyquist band of our ADC). Adding the filter gives the following results:

Amplifier output noise = 1.8 nV/rtHz * 20 V/V * SQRT(30 MHz) = 197 uVADC noise floor: 71.3 dBFS at 1V Full Scale = 272 uV

With the addition of the filter, the amplifier noise is now well below the noise floor of the ADC. When designing the filter, try to model the ADC input capacitance, the amplifier output capacitance and board parasitic capacitances. In addition, the amplifier output pins and the ADC input pins will have approximately 1nH of bond wire inductance. Even with careful modeling, once the circuit is built it will be necessary to carefully measure the filter response and adjust it as needed to tune the filter center frequency. The higher the frequency, the harder it is to accurately model the filter. Also, the smaller components are subject to tolerance errors.

Typically, multiple edges are filtered along to determine which one is the strongest. As the number of detection edges increases, so does the video quality. Therefore, the proper selection of directions is critical to achieving the highest image quality, with special attention being paid to shallow or low-angle directions. The result is sharp detail with less flicker and fewer artifacts.

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