Laird - EMI

<p>Temperature gradients induce mass transport in metal as well. Without an understanding of the local temperature on-chip, electromigration estimates might be off by a large margin.</p>

As you would expect, noise-reduction filtering reduces the effect of the oscilloscope's noise floor. Oscilloscopes are broadband instruments and the higher the bandwidth the higher the noise floor will be. This hardware-induced error component is unavoidable in broadband instruments. With Agilent's 54855A oscilloscope, you can selectively use noise-reduction filtering to improve measurement accuracy, but there is a big tradeoff. When the scope's FIR filter includes noise-reduction filtering characteristics, the bandwidth of the instrument is reduced.

One solution is to use a virtual system prototype (VSP), which is a functionally-accurate and timing-accurate software model of the entire system. Unlike instruction set simulator (ISS)-based prototype solutions — which typically achieve sub-MIPS of performance — today's best VSP prototypes are based on simulation engines that offer both high performance and timing accuracy.

For example, a single processor VSP-based simulation can achieve anywhere between 50 to 200 MIPS, while multi-processor systems with tiered memory structures and multi-level buses can be simulated at 10 to 100 MIPS per processor, depending on the configuration.

DPAM-23-07.0-H-3-2-A_Datasheet PDF

These levels of accuracy and performance mean that VSP-based environments can support the concept of architecture-driven design. First, VSPs by nature support the rapid design of experimental systems and then facilitate architectural exploration and evaluation by supporting rapid iteration of the hardware and software that define the system. Accurate measurements of systems that model real-world behavior under real-world data processing and software workloads allow system architects to make accurate decisions as well as hardware/software tradeoffs early in the design process.

Furthermore, the ability of the VSP to run real software workloads yields invaluable information in guiding the system architects to an optimal architecture. This information includes:

Once an optimal architecture has been determined, the VSP model assumes the mantle of the executable specification. This means that the hardware design teams can use the VSP as a golden reference model” against which they can verify the functionality of the hardware portions of the design.

DPAM-23-07.0-H-3-2-A_Datasheet PDF

But perhaps the most significant advantage of the VSP is that the software development teams can commence work as soon as the system architecture is established — six to 12 months earlier than with sequential engineering processes — and the hardware and software portions of the design can be developed concurrently (Figure 2b).

DPAM-23-07.0-H-3-2-A_Datasheet PDF

Front-end versus back-end loading

By their very nature, conventional (sequential) design environments are back-end loaded in terms of engineering resource requirements and risk. By comparison, a VSP-based, architecture-driven design methodology is front-end loaded, which serves to reduce the peak resources deployed, reduce the total resources deployed, reduce the project risk factors, and shorten the total development time

Design Challenges The need to eliminate the possibility of spontaneous MOSFET turn-on as a result of the threshold voltage being pushed too low results in a dilemma for designers. Usually it is an objective to keep the MOSFET drive circuitry as simple and inexpensive as possible, and this dictates the choice of devices that can switch from 0 to 5V (or higher, depending on the rDS(on) rating of the device used) rather than switching from 5V to a negative value (to keep the MOSFET securely off). As long as there is no inductive load, and provided only low levels of current need to be switched, this solution is perfectly adequate.

The situation changes when high currents and high inductivities, such as those found in electric power steering (EPS) systems, are involved. In such applications, the intrinsic diode of the MOSFET is used, and the current flowing in a reverse direction through the MOSFET may induce a voltage spike greater than the threshold voltage at a given die temperature. This can possibly turn on the MOSFET, even when the gate is at 0V. The risk of this happening increases as die temperatures go up.

Plots of threshold over temperature for same dice but different threshold levels are shown below.

The relationship described above is best illustrated by a comparison between two actual MOSFET devices. For this purpose, we'll compare the SUM110N04-2m3L, with threshold voltages of 1V minimum and 2.1V typical at 25C, and the SUM110N04-2m7H, for which the comparable numbers are 2.5V minimum and 3.4V typical. Both devices are packaged in the same thermally-enhanced D2 PAK and both have the same die size, meaning that their thermal conditions will be equal. Both devices, moreover, are built using the same process technology, signifying that their threshold voltages will decrease over temperature in the same way.

Current running through the device increases the die temperature to 150C. At this point the threshold voltage reaches its typical level, as per the following formula:

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