NETANYA, Israel — IBM Corp. (Armonk, New York) signed a new industrial cooperation agreement with Israel's Industrial Cooperation Authority. The new agreement follows a previous one signed in 1996 and it regulates the relations of IBM with Israeli organizations and government entities.

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Monolithic Power Systems

<p>The round was led by an un-named world class investment company”, with participants including previous backers Intel Capital and JK&B Capital.</p>

NETANYA, Israel — IBM Corp. (Armonk, New York) signed a new industrial cooperation agreement with Israel's Industrial Cooperation Authority. The new agreement follows a previous one signed in 1996 and it regulates the relations of IBM with Israeli organizations and government entities.

What appears to set the electrically active gate length is the bird's beak formed where the sidewall spacer meets the TIL. SI analysis concluded that this bird's beak is the result of TIL and high-k etches undercutting the polysilicon. Reoxidation of the polysilicon sidewall prior to silicon nitride spacer formation exacerbates the undercut. For the metal gate deposited into the trench, there is a thick, relatively low-k path toward the channel at this point that obviously could not electrically influence charge carriers in the region directly underneath the bird's beak.

The critical portion of the metal gate could also be the TIL itself. Because this layer is composed of the same work function metal as the gate-last layer, perhaps its edge defines the metal-gate length. Fortunately, the edge of the TIL layer approximately aligns with the bird's beak above it, so the choice of measurement point will not affect the value you get for LG .

RLR07C4303GSRE8_Vishay Dale_Through Hole Resistors

The punch line to all of this is that the gap between the gate trench edge and the electrically active edge of the work function metal (whether first or last) accounts for somewhere between 8 and 10 nm. And that appears to explain the difference between Intel's reported value for LG and what the rest of us have been looking at.

Despite its cure for leakage power, adding hafnium creates headaches for the process integration engineer. Intel avoided hafnium's downsides (threshold voltage pinning and reduced carrier mobility) by creating a silicon oxide (or possibly oxynitride) bottom interface layer (BIL) between the silicon substrate and the HfO2 layer. The BIL not only gets hafnium into the gate stack but gives the process engineer one more tuning knob. Because the gate dielectric's influence on the transistor channel and electrical performance is a function of the individual contributions of the various layers, threshold voltages can be controlled by varying the BIL thickness for different transistor applications.

Design-for-manufacturabiltyProcess variability, and designing for it, is a hot topic as problems such as line-edge roughness and random dopant fluctuations become more problematic at 45 nm. This was addressed in Intel's second IEDM 2007 presentation, in which Kelin Kuhn discussed improving yield by process improvements as well as design changes. The SRAM cell illustrated Kuhn's point as she showed the evolution from 90-nm to 45-nm design. The tall” cell layout used at 90 nm was replaced with a wide” cell at 65 nm. The 65-nm cell design improved dimension control and variability by aligning the polysilicon in a single direction and removing the corners in the active area patterns. At 45 nm, Intel's process removed dog bone” and icicle” shapes by employing only square end caps. These uniform structures are also easier to fill reliably in the gate-last process.

RLR07C4303GSRE8_Vishay Dale_Through Hole Resistors

Intel continues to use 193-nm dry lithography at 45 nm. Restricted design rules create structured” gate layouts, as Kuhn mentioned in her discussion of the SRAM cell. This DFM technique of uniform, regular arrangement of metal gates improves yields for the advanced HKMG technology without requiring investment in new immersion tooling. Creating strictly rectangular gate patterns did require an extra step, because double-patterning was used for the sacrificial polysilicon layer.

Many features of Intel's 65-nm process remain in evolved forms. Third generation” strained silicon is used that is structurally similar to the embedded SiGe PMOS of Intel's 65-nm process. Nickel salicide is also used again at 45 nm. Intel employs dual damascene copper up to metal nine. A SiCN barrier with carbon-doped oxide creates the low-k interlevel dielectric integration scheme.

RLR07C4303GSRE8_Vishay Dale_Through Hole Resistors

LARGO, FL &#8212 Res-net Microwave Inc., a subsidiary of Electro Technik Industries, Inc., is introducing a miniature zero-bias Schottky diode detector to their current line of microwave and RF products.

The Schottky diode is an order of magnitude faster than conventional PN diodes making them ideal for RF and microwave applications. It has a low junction capacitance and excellent sensitivity and bandwidth. This makes the detector especially suited for navigation systems, wireless networks and devices, security/alarm systems, radar, and radio controlled transmitters.

Despite the excitement for thin-film products, the market is becoming overcrowded with a slew of startups with unproven technologies. In the CIGS segment alone, DayStar, HelioVolt, Iset, Miasole, Nanosolar, Solyndra and others have emerged.

GSE claims to be ahead of its new rivals, many of which have been unable to get their products out the door. Founded in 1996, GSE began to produce its first CIGS-based solar cells in 2004.

While other companies produce CIGS on glass, GSE claims to be the only company with CIGS on flexible materials. GSE uses a roll-to-roll” and a vacuum deposition manufacturing process, enabling lightweight, flexible cells.

The company's proprietary process claims to produce among the highest efficiency” solar cells in the thin-film market. In comparison, high-flying First Solar, which uses a cadmium telluride (CdTe) technology, is said to have efficiencies in the 10 percent range. First Solar's average module conversion efficiency is 10.5 percent as of September 2007, according to that company.

Conventional cells have higher efficiencies, but these products are becoming more expensive due to the soaring costs of polysilicon materials. SunPower Corp. has demonstrated a cell at efficiencies of over 20 percent.


Nemerix SA (Manno, Switzerland), founded in April 2002, is a venture capital backed fabless semiconductor company specializing in global positioning by satellite integrated circuits, software and firmware. Cadence Design Systems Inc. was one of the investors in a $31 million VC round that was announced in September 2005.

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