Vishay / Huntington Electric, Inc.

<p>Europe's lead-free initiative lies with the European Council Directive on Waste from Electrical and Electronic Equipment. This directive calls for hazardous material substitutions to be implemented by the beginning of 2008.</p>

Under peak transmit power, the power amplifier requires a 3.4-V supply rail and will draw between 300 mA and 600 mA (2,040 mW). Under the lowest transmit power, close to a basestation and transmitting voice only, the power amp draws as little as 30 mA with supply voltage between 0.4 and 1 V (12 mW). This corresponds to power consumption of 2,040 mW maximum and 12 mW minimum.

Micron said it will continue, restructure or repay all of KMT's debt at the closing of the transaction. Those costs are projected to be 37 billion yen ($325 million).

These Web sites offer additional help when designing with programmable logic.

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www.rtrack.com At its Web site, Right Track Corp. offers a general CAD tool for programmable logic. The VPR Placement and Routing system takes as input a circuit netlist and a description of the target FPGA architecture and then outputs a fully implemented circuit. The CAD tool can also provide important parameters such as the maximum speed of the circuit and an estimate of the area used on the target FPGA. The software was originally developed at the University of Toronto.

www.ictpld.com/pod/podindex.htm Integrated Circuit Technology Corp. offers a system-on-chip (SoC) design tool called Programmability-on-Demand, designed to offer designers product differentiation and product upgradability while reducing the time-to-market and other risks associated with SoC design. The company says that it can provide complete solutions for embedding E2PROM nonvolatile memory and programmable logic into SoC devices.

http://xputers.informatik.uni-kl.de/papers/paper091-1.html Research at the University of Kaiserslautern (Kaiserslautern, Germany) looks at the memory management issues that crop up in configurable-computing design. The researchers offer a new approach to two-dimensional memory management based on analyzing computational sequencing patterns and their interaction with storage methods.

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www.edc.ncl.ac.uk/~ianb/codesign.html The Engineering Design Center at the University of Newcastle, England, has developed an interesting approach to controlling system design using FPGAs. The concept is to devise reactive systems” by including system feedback in the design process. The hardware then evolves to handle the typical computational control problems in real-time.

http://splish.ee.byu.edu/docs/papers1.html The Reconfigurable Logic Group at Brigham Young University in Utah has a comprehensive group of papers on application of FPGAs to embedded and signalprocessing jobs. Signal processing in exotic areas such as radar and sonar are treated, as well as other high-performance issues such as the design of finite-field multipliers or microprocessors.

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MANHASSET, N.Y. — A group of venture capitalists, executives and entrepreneurs have announced the formation of a technology operating company that aims to put a business head” on the body of corporate R&D labs.

X-Laboratories (Malibu, Calif.) will work to ferret out, develop and commercialize untapped technologies hidden within corporate research facilities. The company will partner with corporate research labs to filter, refine and launch technologies for select growth markets and then either license the technologies and market know-how to other companies or spin out such efforts itself.

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The major product announcement this week by Tektronix about their MDO3000 instrument once again made me think of multifunction test instruments and their attributes, which can be both useful and a headache. (See It’s an oscilloscope and…)

(Note that Tektronix is not the only vendor to offer combined units. It’s just that their recent news spurred my thinking.)

There are several levels at which test instrumentation can be combined:

Another challenge, Hauck said, lies in mapping software, which requires tools far different from the hardware compilers and CAD algorithms typically used in ASIC-based SoC designs-partly because of the constraints that FPGAs impose, but also because of the types of users the high-density FPGA offerings hope to attract.

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