Mode Electronics

<p>Apart from the typical Spi-4.2 method of a sink FIFO status update for flow control, the interface logic (using information from the NPU packet-scheduler) can dynamically configure the calendar/max burst through the hitless bandwidth reprovisioning. This is generally based on source FIFO traffic conditions. Most problems with respect to Spi-4.2 interface efficiency in terms of bandwidth utilization, scheduling-latency FIFO provisioning, and responsiveness to port status and data-availability can be solved with the proper system design.</p>

Deploying security solutions that can support multiple security functions in a single box simplifies network operations and reduces capital equipment acquisitions costs required to secure both the network and the services it carries.

About the Author Sophia Scoggins is a software system engineer in the Packet Voice and Video Group. Scoggins joined Texas Instruments in 2003. Before TI, she held engineering and product marketing positions at such companies as Nortel Networks, Siemens Efficient Networks, Coppercom and UMKC. Scoggins holds a Ph.D. in IE from TTU. She is a Ph.D. candidate with an MS degree in telecommunications, networking, and computer science from UMKC. She also holds an MBA from ENMU, and B. Law from Taiwan. Sophia has two international patents, is the author of a textbook on Open Internetworking with OSI, and has written over 50 conference, seminar, and journal papers. She can be reached at:

The light-weight, long-lasting, high-performance attributes of cellular phones and laptop computers, among other equally impressive portable devices currently in the marketplace, are responsible for igniting the overwhelming growth of the battery-powered electronics industry. The demand for smaller and longer lasting solutions, in fact, is only increasing, and key to this success is the battery, which can range from single-use alkaline and zinc-air to rechargeable nickel-cadmium, nickel-metal hydride, lithium-ion, and lithium-polymer technologies. Unfortunately, however, advancements in circuit and system integration have outpaced energy and power density improvements in the battery. Consequently, as batteries conform to the size constraints of portable applications, capacity and output power are necessarily compromised.

CMF551K2000BEEB_Vishay Dale_Through Hole Resistors

Degradation in battery performance over time not only affects functionality but also operational life, proving inadequate the traditional assumption that the battery is an ideal voltage source. Including the effects of the battery on state-of-the-art systems during the design phase is therefore of increasing importance for optimal life and performance. The problem is securing a suitable Cadence-compatible model.

Battery Models

State-of-the-art electrical models for batteries are either Thevenin-, impedance-, or runtime-based. Thevenin- and impedance-based models, shown in Figures 1(a)-(b), assume both open-circuit voltage and capacity or state-of-charge (SOC) are constant and approximate loading and ac/transient effects with an impedance network of passive devices for transient response and/or curve-fitting impedance blocks (for example, ZAC ) derived from electrochemical-impedance spectroscopy experiments for ac response. Both these models concentrate on either transient or ac response, but neither considers temperature, lifetime limits, or steady-state open-circuit voltage variations (that is, DC effects). Reported runtime-based models (Figure 1(c)), on the other hand, predict operational life and steady-state variations of the open-circuit voltage, but at the cost of complexity and therefore increased simulation time, which is why an impedance matching network for predicting transient and/or ac response is usually forfeited, yet this is exactly what is needed to fully comprehend the degrading characteristics of the battery.

CMF551K2000BEEB_Vishay Dale_Through Hole Resistors

Simplifying the battery model…

CMF551K2000BEEB_Vishay Dale_Through Hole Resistors

The basic requirements of the model are to predict lifetime and steady-state (or DC), ac, and transient response performance, in other words, combine the attributes of Thevenin-, impedance-, and runtime-based models, but in a more compact and electrically meaningful fashion, more like the one presented in Figure 2 [1]. The proposed model is separated in two, lifetime and voltage-current (I-V). The former is a simplified version of the runtime-based model and the latter a straightforward expansion of the Thevenin-based scheme.

While such techniques improve dynamic power, leakage during the off-state will remain a problem until a high-k dielectric is incorporated, Meyerson said. He believes that high-k may arrive first for chips that value low leakage over high performance. For high-performance chips, companies will continue to endure high leakage levels until a thinner electrical oxide is developed, he said.

The chip industry is in a period of pent-up demand,” Meyerson said. Gate oxides, made with nitrided silicon dioxide, have stalled at roughly the 1.2-nm physical thickness, which translates into 1.8 to 2.2 nm of electrical or effective oxide thickness (EOT).

Oxide has not scaled up that well, and the company that solves the oxide problem-taking electrical oxide thicknesses of 18 to 22 angstroms down to 10-will generate a tremendous boost in performance while improving the leakage current,” said Meyerson. Until then, he said, the industry will be in a state of volatility” as physical dimensions are scaled, with clock frequency plateauing over time.”

Some improvements in gate oxide hardening”-adjusting the nitrogen profile closer to the surface-have been realized, but hardening mainly improves the reliability of the oxide and does relatively little for performance, Meyerson said.

Classical scaling-just making it smaller to go faster-died at 130 nm. Leakage forces you to do other things to keep power from getting out of control,” he said. Some require innovations, such as strained silicon and new dielectrics. We are experimenting with a whole variety of materials. But we are not scaling any longer. We are not in the neighborhood of where we need to be in terms of actual T inversion,” a measure of the electrical-oxide thickness when a transistor is in the inversion state.

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In the long run, however, leveraging pattern-matching capabilities combined with fine-grained traffic management features implemented in network processors is a more effective security approach compared with depending on multiple ASIC security devices, each specializing in only one area of deterrence.

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