TE Connectivity Potter & Brumfield Relays

<p>You have this funny dynamics where the IC companies don't care very much about new packaging technologies, but their customers are driving them to it. Their customers are driving them to higher-cost packages, which make the ICs more valuable in the systems, but no one want to pay more for it.</p>

But you can become so enamored of these softer attributes that you neglect to look long and hard at what solid data is available and then reconcile the data with your feelings. Don’t dismiss one or the other, but work to understand where they agree and why, and just as vital, where they differ and why that might be so.

Red Hat and Ericsson are also joining forces to develop new services for network operators. The new Ericsson/Red Hat technology partnership will make it possible for service operators to offer a number of remote-management services across the Internet, including remote configurations, updates and repairs,” said Knutilla.

Ericsson will work with Red Hat to establish open technologies such as the latest embedded Red Hat GNU development tools, which will be made freely available to developers through Red Hat's Web site.

FSI-110-06-S-D-AB_Datasheet PDF

Red Hat's software design team and Ericsson's hardware development team are already working together to integrate the initial Web Phone product, said Knutilla.

In a recent article , Rajeev Madhavan, Chairman and CEO of Magma Design Automation, outlined changes that design teams are grappling with as they face multiple challenges in the designs they have to deliver. It is indeed true that designs are going to have to meet the following requirements: increasing levels of integration of analog and digital components on the same silicon substrate, lower power consumption targets (both standby and operational) and higher performance requirements. It is also true that these have to be done within compressed design schedules and with smaller design teams spread out all over the world.

FSI-110-06-S-D-AB_Datasheet PDF

In addition to these challenges design teams also have to worry about integration of their chips inside a package (single die, stacked die, MCM, SiP, etc), and on the board. This has to be done for power and signal integrity to ensure robust power supply and signal transmission for high performance designs. Additionally, cooling system design and EMI/EMC compliance are two key system-level design targets that require integrated chip-package-PCB analysis. So not only are designers challenged with chip-level integration, they also have to look at chip, package and PCB integration and design convergence.

As the engineering management in design houses target ways to reduce power in their designs, integrate multiple different types of IP in their silicon and ensure highest performance for their systems, they have to look at ways their different design groups (RTL, analog/IP design, SoC physical design, package/PCB design) work together. These design groups have different data formats, follow different design and analysis methodologies and target different goals. Adding to the complexity, these design groups may be separate and distinct organization wise.

FSI-110-06-S-D-AB_Datasheet PDF

Given the compressed schedules design teams have to work with, they need integrated solutions that can not only help them optimize and sign-off for these design targets (power, integration and speed) but also help them work together as one design entity even if they may be separated by corporate or data/flow/methodology boundaries. What they need are analysis flows that they can use throughout their design cycle optimizing and verifying the designs at every stage and feeding data to the other stages and design flows.

As Rajeev mentioned in his article , power has to be considered throughout the design process. But this is not only true for mobile devices where low power targets are required but also for high performance designs where performance per Watt is the deciding factor. Most of the optimizations that can be done to the design for power reduction are mostly achieved early in the design process where targeted changes can not only have the most impact but also are easier to implement. But changes done to the netlist at this stage to achieve power reduction can and often introduce unwarranted effects on the power integrity of the design later in the design process. Hence, a design for power methodology is required in which power analysis and reduction is started from early in the design process (RTL stage). Then, as the design progresses, power consumption at the block and chip level is monitored through regular regressions and checked as a design target. Violations are flagged and resolved as they appear preventing unwanted surprises later. As one progresses to the physical design stage, information from the RTL simulations are passed to provide more coverage for the gate-level design verification and sign-off.

Cerent's ONS 15454 product, which provides Sonet links for the metropolitan market, has lots of traction,” Russo said. Arguably, it's been the most successful of Cisco's optical acquisitions. For dense wave-division multiplexing in the network core, the ONS 15800 derived from Pirelli is shipping for the Sonet OC-48 (2.5 Gbit/second) and OC-192 (10 Gbit/s) speed grades.

Switching in Cisco's optical-networking plans is handled by the ONS 15900, based on Monterey technology. This box hasn't begun volume shipping but is in multiple trials, and certain customers should be disclosed within 90 days, Russo said.

Russo denied that Cisco was having problems with the Monterey and Pirelli acquisitions, as has been rumored. Monterey, in particular, had had its manufacturing schedules redrawn, a routine step following a merger, Russo said.

When you're a startup, you are willing to take more risks with your products,” he said. We reset those schedules. We communicated them to our customers. We didn't communicate them to anybody else. My fault.”

The Qeyton acquisition was targeted for providing dense WDM in the metropolitan ring. Russo said that a satellite” box from Qeyton was being prepared, built for easy installation, a key requirement in the metro space, he said.

The company said its wafer fab sales reflected continued strong demand, primarily from Texas Instruments Inc. for digital signal processor wafers. The Amkor's Anam foundry unit averaged 24,000 eight-inch equilvant wafer starts per month during the second quarter, as the Korean fab continued its ramp toward a planned capacity of 30,000 wafers per month by the end of 2000, said the West Chester company.

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