<p>Meanwhile, with the IEEE 1364 group soliciting donations from all sources, Cadence Design Systems Inc., a System-Verilog 3.1 skeptic, donated language extensions last week for constrained and random testbenches. These compete with a handful of today's SystemVerilog 3.1 constructs, Mitch Weaver, vice president of marketing for Cadence's functional verification group, acknowledged.</p>

All this assumes, however, that call centers use objective and sound metrics. But benchmarking, like medicine a century ago, appears to be more art than hard science. While call centers are dropping cost-based metrics in favor of profit-based metrics, as of yet there is no industry-wide agreement on how to define or measure these metrics.

Rupert Baines, vice president for marketing told this is fundamental to what we have been doing. We are clearly more than just than a chip company. Our value is in systems expertise and being able to work with companies at the high end on very complex tasks, and this is just a way of 'productising' that strategy.

Baines said development times for a basestation can be up to 24 months or more, with budgets of many tens of millions of dollars: this solution makes it possible to reduce these by up to 50%. It is aimed primarily at those who want to get into the wireless infrastructure business but do not possess the expertise to do it all themselves.”

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He added that as well as manufacturers, the reference patform is ideally suited to operators, system development houses and research organisations wishing to test out new features.

PicoChip CTO & Co-founder, Doug Pulley, said, ” We can now supply OEM customers with a complete WCDMA software reference design, fully compliant and tested. Our software-defined basestation removes the need to worry about obsolescence, interoperability or being trapped into out-dated standards — while reducing system cost and bill of materials. What is more, because this is a software-based platform, customers retain the crucial ability to add proprietary elements, to use their own algorithms and to include their own IP.”

The hardware is based around picoChip's technology platform of picoArray devices. The system is capable of supporting the full set of 3G voice, data and video services. The system complies with Release 4.2.0 (Sept 2001) of the standard (the most common revision for current deployment and for interoperability with handsets) and has been fully tested to TS25.215 and TS25.104. Support for Release 5 (including HSDPA) is now under development for release later this year. Versions are available for both macro-cells and micro-cells.

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Pulley, added, This is the first in a series of system level products that includes different protocols and 3G test equipment. Future releases include HSDPA, TD-SCDMA and 802.20.

SANTA CLARA &#151 Negevtech hat ein Wafer-Inspektionssystem vorgestellt, das für den Einsatz in der Fertigung von ICs mit Hilfe von 90-nm- und 65-nm-Prozessen optimiert ist. Laut Hersteller handelt es sich dabei um das weltweit erste System, das Hellfeld- und Dunkelfeld-Techniken kombiniert.

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Das Produkt mit der Typenbezeichnung Negevtech 302 nehme im Vergleich zu herkömmlichen Hellfeld-Systemen nur die Hälfte des Platzes im Reinraum ein. Das führe im Vergleich zu existierenden Systemen zu einem Cost-of-Ownership, das um den Faktor 10 niedriger sei, verspricht der Anbieter.

Drei Anforderungen stellen die Hersteller von ICs an heutige Inspektionssysteme: Sie sollen sämtliche kritischen Defekte aufspüren und dabei höchsten Durchsatz und ein niedriges Cost of Ownership bieten. Für ICs, die mit Hilfe von 65-nm-Prozessen gefertigt werden, gibt es derzeit kein System, das diesen Anforderungen genügt”, erläutert Dr. Gadi Neuman, Managing Director von Negevtech. Deshalb haben wir eine neue Technik entwickelt, die eine bessere Performance im Bereich der Hellfeld- und Dunkelfeld-Techniken bietet. Die Negevtech 302 ist einfacher aufgebaut und daher kostengünstiger als die heute existierenden Inspektionssysteme.”

At the gate and transistor level a wide range of other techniques are employed, beyond just using a much more power effiecient CMOS process. These include partitioning separate voltage and clock domains; selective scaling of voltage and frequency; gating different voltage levels to different blocks; and decreasing capacitive and DC loading on outputs, amongst other techniques.

Despite the availability of such an array of solutions, or perhaps because of the increasing complexity that they bring to a design, increasingly some designers are finding that the answers to some of their design dilemmas may lie in re-evaluating the understood and predictable synchronous methodologies and looking for other alternatives.

Async support

Now receiving a second look are a whole set of alternative asynchronous self-clocked, locally clocked and self-timed design methodologies. Contributors to this week's In Focus take a look at the growing concern in building synchronous circuits and the promise and practicality of asynchronous design.

Asynchronous techniques also got considerable coverage in the Mead-Conway text, except for very specific design problems in which nothing else would work. Still, most designers, such as online contributor Shekhar Borkar, Intel Fellow and director of circuit research at Intel Corp.'s Microprocessor Research Lab (Hillsboro, Ore.), rule out its use because the circuits designed with them have not been fast enough, are not compatible with existing EDA tools and require unfamiliar design flows.


The CEB grew out of a need for such standards. BenchmarkPortal and Convergys conducted a needs assessment study across the call center market, which indicated a lack of standard customer satisfaction benchmarking data.

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