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<p>Two prototype IBM supercomputers now rank as the world's fourth and eight most powerful systems, up from the 73rd spot in the rankings six months ago. The IBM Blue Gene/L systems are the most likely to unseat NEC Corp.'s Earth Simulator as the world's most powerful computer when they are installed and fully configured with up to 64,000 custom PowerPC processors probably next year, said Erich Strohmaier, a computer scientists at Lawrence Berkeley National Labs who compiled the Top 500 supercomputer list.</p>

The move will also eliminate additional traces on the motherboard needed for control signals, making the QBM modules truly able to plug and play into DDR-based systems. The company has also decided to use a Jedec standard PLL instead of a customized version.

June 2004 – Nihon Dempa Kogyo (NDK) announces the availability of the NV7050SA series, a miniature Voltage Controlled Crystal Oscillator (VCXO) available in the frequency range of 1.544~180MHz. The miniature hermetically sealed 6 pad SMD package measures only 7.0×5.0mm with a thickness of only 1.6mm. The NV7050SA delivers a CMOS output in the 1.544~80MHz frequency range and a PECL output in the 80~180MHz frequency range. This VCXO has an operating temperature range of -40 to +85°C with a frequency stability of 50ppm maximum and an absolute pull range of 100ppm. It operates on a supply voltage of +3.3VDC while consuming 30mA maximum (CMOS) and 70mA maximum (PECL). The NV7050SA has a control voltage of 0~3.3VDC with a load of 15pF (CMOS) and 50 ohms (PECL).

Applications for the NV7050SA include telecom and enterprise networks, base stations, and instrumentation.

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Cost for the NV7050SA series is under $5.00 each in 2,000 piece quantities. Engineering samples can be ordered by going to the NDK order site (you will need to register), or by calling 800-NDK-XTAL (635-9825). Volume production will begin in October of 2004. A complete set of technical data and application engineering support is available, by calling 800-NDK-XTAL (635-9825), visiting www.ndk.com, or email .

Chandler, Ariz.– Microchip Technology Inc. has expanded its line of PIC flash microcontrollers with the launching of twelve devices.

Included are four 64- and 80-pin devices targeting cost-constrained applications requiring additional I/O, such as industrial, computing, telecommunications and consumer. These PIC18F microcontrollers feature 8 or 16K bytes of program memory. The remaining eight devices in 28- and 40/44-pin packages target high-end applications requiring additional memory in low pincounts. These units feature up to 64K bytes of program memory. All devices employ nanoWatt Technology for power management.

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Designers of embedded control applications have a growing need for 8-bit microcontrollers with increased I/O, balanced with a requirement to consume less power, over a broad range of applications. These new PIC18F microcontrollers help solve these design concerns with up to 70 pins of I/O, 8 or 16K bytes of Flash program memory, 768 bytes of RAM and nanoWatt Technology low-power modes.

Microchip is increasing its presence in the 64- and 80-pin space of the 8-bit microcontroller market,” said Ganesh Moorthy, vice president of Microchip's Advanced Microcontroller and Memory Division. These new Flash PIC microcontrollers provide designers with cost-effective high pincount options.”In addition to offering maximum I/O flexibility, these new PIC microcontrollers offer the programming versatility of Flash memory.

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Example applications that could benefit from the increased I/O present in the PIC18Fxx10 include: building security systems, appliance controls, video control panels, home automation systems, and data collection for multiple sensors. Additionally, with the nanoWatt Technology, these microcontrollers offer power-managed modes that make them ideal for battery and low-power applications.

Additional features include external clock with up to 40 MHz (10 MIPS), 32 Khz to 32 MHz (8 MIPS) internal oscillator, fail-safe clock monitor, wide voltage range of 2.0 @ 5.5 volts, and a -40C to +125C temperature range, In-Circuit Serial Programming (ICSP), 10-bit analog-to-digital converter with up to 12 signal channels and 100k samples-per-second, two analog comparators with programmable brownout detect and programmable low-voltage detect, SPI, I2C and two USARTs (support RS485, RS232, LIN) and three Capture Compare PWM modules.

In response, several ATE houses claim that they have developed new and open” testers, based on a modular architecture. NPTest, Agilent, LTX and Teradyne are pushing their respective ATE machines as open systems.

Intel Corp. recently confirmed that it has taken deliveries on a new and modular IC tester from Japan's Advantest Corp. Intel is procuring Advantest's T2000, a modular, high-performance IC-test system, built around the Open Semiconductor Test Architecture (Openstar) (see June 18 story).

Advantest has developed the T2000 IC tester especially for Intel and other chip makers. Two years ago, Intel, Advantest, Motorola and others co-founded the Semiconductor Test Consortium Inc. (STC). STC's aim is to devise an open architecture” for ATE, which would enable the development of plug-and-play” modules, thereby addressing the soaring costs of IC test.

The trouble with open ATE is that there are still too many platforms in the marketplace, according to analysts. Even the ATE houses see the handwriting on the wall. A lot of our customers want to do more business with fewer suppliers,” said David Ranhoff, president and chief operating officer at Credence.

Malvern, Pa. — Two new families of precision thin-film resistor networks from Vishay Intertechnology Inc. extend the ratio tolerance to a new industry-low of 0.01% in SOT-23 and 8-pin SOIC packages. The MPM and ORN matched-pair and quad resistor networks offer designers an alternative to technologies such as wirewound and hermetic packaging that was previously required to maintain a low tolerance. These devices are designed for instrumentation amplifiers, precision voltage dividers and bridge network circuitry.

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It is possible to calculate the passive network efficiency, ηpass , for a necessary PER and a given available inductor Qind . Figure 1b shows plots of Ω vs. PER for several different Qind for a single section network of Figure 1a .

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